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Difference between revisions of "mediatek/helio/mt6757"
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− | '''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports dual-channel | + | '''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6. |
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== Cache == | == Cache == | ||
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}} | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}} | ||
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type= | + | |type=LPDDR4X-3200 |
− | |||
|ecc=No | |ecc=No | ||
|max mem=6 GiB | |max mem=6 GiB | ||
|controllers=1 | |controllers=1 | ||
|channels=2 | |channels=2 | ||
+ | |width=32 bit | ||
|max bandwidth=23.84 GiB/s | |max bandwidth=23.84 GiB/s | ||
|bandwidth schan=11.92 GiB/s | |bandwidth schan=11.92 GiB/s |
Revision as of 16:49, 12 July 2017
Template:mpu Helio P20 (MT6757) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and set to be launched in 2017. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 16 nm process, operates at up to 2.3 GHz and supports up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the Mali-T880 IGP operating at 900 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.
Contents
Cache
- Main article: Cortex-A53 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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Wireless
Wireless Communications | |||||||||||||
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2G |
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3G |
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4G |
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Image
This section is empty; you can help add the missing info by editing this page. |
Video
This section is empty; you can help add the missing info by editing this page. |
Audio
This section is empty; you can help add the missing info by editing this page. |
Utilizing devices
This list is incomplete; you can help by expanding it.
Facts about "Helio P20 (MT6757) - MediaTek"
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus type | AMBA 4 AXI + |
core count | 8 + |
core name | Cortex-A53 + |
designer | MediaTek + and ARM Holdings + |
family | Helio + |
first announced | September 22, 2016 + |
first launched | November 2016 + |
full page name | mediatek/helio/mt6757 + |
has 2g support | true + |
has 3g support | true + |
has 4g support | true + |
has csd support | true + |
has dc-hsdpa support | true + |
has e-utran support | true + |
has ecc memory support | false + |
has edge support | true + |
has gprs support | true + |
has gsm support | true + |
has hsupa support | true + |
has lte advanced support | true + |
has td-scdma support | true + |
has umts support | true + |
instance of | microprocessor + |
integrated gpu | Mali-T880 + |
integrated gpu base frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 2 + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | November 2016 + |
manufacturer | TSMC + |
market segment | Mobile + and Embedded + |
max cpu count | 1 + |
max memory | 6,144 MiB (6,291,456 KiB, 6,442,450,944 B, 6 GiB, 0.00586 TiB) + |
max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex-A53 + |
model number | P20 + |
name | Helio P20 + |
part number | MT6757 + and MTK6757 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
series | Helio P + |
smp max ways | 1 + |
supported memory type | LPDDR4X-3200 + |
technology | CMOS + |
thread count | 8 + |
used by | Alcatel Idol 5S +, Blackview BV9000 PRO +, Elephone P20 +, Elephone Z1 +, InnJoo Pro 2 +, Meizu E2 +, Meizu X +, Sony Xperia XA1 +, Sony Xperia XA1 Ultra +, UMiDIGI S +, UMiDIGI Z1 +, UMi Plus Extreme +, Samsung On Max +, MEIIGOO M1 +, CAT S41 +, Sony Xperia XA1 Plus +, Maze Alpha +, UMiDIGI Z1 Pro +, Samsung J7 max +, Doogee S60 +, Lenovo K8 +, Samsung J7+ +, Vernee MIX 2 +, Bluboo S1 +, Maze Alpha X +, Gome K1 +, Vargo VX3 + and Blackview BV8000 PRO + |
user equipment category | 6 + |
word size | 64 bit (8 octets, 16 nibbles) + |