From WikiChip
Difference between revisions of "intel/core i3/i3-6100u"
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== Graphics == | == Graphics == | ||
− | {{integrated | + | {{integrated graphics |
− | | gpu | + | | gpu = HD Graphics 520 |
− | | device id | + | | device id = 0x1916 |
− | | displays | + | | designer = Intel |
− | | frequency | + | | execution units = 24 |
− | | max frequency | + | | max displays = 3 |
− | | | + | | max memory = 32 GiB |
− | | output edp | + | | frequency = 300 MHz |
− | | output dp | + | | max frequency = 900 MHz |
− | | output hdmi | + | |
− | | output vga | + | | output crt = |
− | | output dvi | + | | output sdvo = |
+ | | output dsi = | ||
+ | | output edp = Yes | ||
+ | | output dp = Yes | ||
+ | | output hdmi = Yes | ||
+ | | output vga = | ||
+ | | output dvi = Yes | ||
+ | |||
| directx ver = 12 | | directx ver = 12 | ||
| opengl ver = 4.4 | | opengl ver = 4.4 | ||
Line 126: | Line 133: | ||
| max res vga freq = | | max res vga freq = | ||
− | | intel quick sync | + | | features = Yes |
− | | intel intru 3d | + | | intel quick sync = Yes |
− | | intel insider | + | | intel intru 3d = Yes |
− | | intel widi | + | | intel insider = |
− | | intel fdi | + | | intel widi = |
− | | intel clear video | + | | intel fdi = |
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = Yes | ||
}} | }} | ||
+ | {{skylake hardware accelerated video table|col=1}} | ||
== Features == | == Features == |
Revision as of 20:36, 3 July 2017
Template:mpu Core i3-6100U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable-down TDP of 7.5 W. This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features
Facts about "Core i3-6100U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i3-6100U - Intel#io + |
device id | 0x1916 + |
has ecc memory support | false + |
integrated gpu | HD Graphics 520 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
supported memory type | DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 + |