Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i3/i3-6100u"
| Line 56: | Line 56: | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=2x32 KiB | |l1i break=2x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |||
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=2x32 KiB | |l1d break=2x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=512 KiB | |l2 cache=512 KiB | ||
|l2 break=2x256 KiB | |l2 break=2x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=3 MiB | |l3 cache=3 MiB | ||
| − | |l3 | + | |l3 break=2x1.5 MiB |
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 18:48, 3 July 2017
Template:mpu Core i3-6100U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.3 GHz. The i3-6100U has a TDP of 15 W with a configurable-down TDP of 7.5 W. This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
Cache
- Main article: Skylake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Graphics
| Integrated Graphic Information | |
| GPU | Intel HD Graphics 520 |
| Device ID | 0x1916 |
| Displays | 3 |
| Frequency | 300 MHz 0.3 GHz
300,000 KHz |
| Max frequency | 1 GHz 1,000 MHz
1,000,000 KHz |
| Max memory | 32 GiB 32,768 MiB
33,554,432 KiB 34,359,738,368 B |
| Output | DisplayPort, Embedded DisplayPort, HDMI, DVI |
| DirectX | 12 |
| OpenGL | 4.4 |
| OpenCL | 2.0 |
| HDMI | 1.4a |
| DP | 1.2 |
| eDP | 1.3 |
| Max HDMI Res | 4096x2304 @24 Hz |
| Max DP Res | 4096x2304 @60 Hz |
| Max eDP Res | 4096x2304 @60 Hz |
| Intel Quick Sync Video | |
| Intel InTru 3D | |
| Intel Insider | |
| Intel WiDi (Wireless Display) | |
| Intel Clear Video | |
Memory controller
| Integrated Memory Controller | |
| Type | LPDDR3-1600, LPDDR3-1866, DDR4-1866, DDR4-2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | No |
| Max bandwidth | 34,100 MB/s |
| Max memory | 32,768 MB |
Expansions
Features
Facts about "Core i3-6100U - Intel"
| device id | 0x1916 + |
| has feature | integrated gpu + |
| integrated gpu | Intel HD Graphics 520 + |
| integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
| integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
| integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |