Semiconductor & Computer Engineering
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Difference between revisions of "arm/armv1"
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{{arm title|ARMv1}} | {{arm title|ARMv1}} | ||
| − | '''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. | + | '''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{armh|ARM1}} and was replaced soon after by the {{armh|ARM2}}. Only a few hundred of those chips were ever fabricated. |
| + | |||
| + | == Overview == | ||
| + | The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a [[program counter]] which is 26 bits in size allowing for an address space of up to 64 MiB of data. | ||
| + | |||
| + | == Registers == | ||
| + | There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}}, all registers are orthogonal with no specific designated purpose. | ||
| + | |||
| + | == Instruction Listing == | ||
| + | The ARMv1 is broken down into 2 classes of instruction: | ||
| + | |||
| + | * [[#load_instructions|Load Instructions]] | ||
| + | * [[#store_instructions|Store Instructions]] | ||
| + | |||
| + | {{isa | ||
| + | | title = ARMv1 ISA | ||
| + | | Syntax | ||
| + | | Description | ||
| + | | Action | ||
| + | | cols = 5 | ||
| + | | listing = | ||
| + | |||
| + | {{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span>}} | ||
| + | {{inst|mn=LDR |col 1=LDR{cond} Rd, address |col 2=Load [[Word]] |col 3 = Rd = [address]}} | ||
| + | {{inst|mn=LDRT |col 1=LDRT{cond} Rd, address |col 2=Load [[Word]], User Mode Privilege |col 3 = Rd = [address]}} | ||
| + | {{inst|mn=LDRB |col 1=LDRB{cond} Rd, address |col 2=Load [[Byte]] |col 3 = Rd = ZeroExtend([address])}} | ||
| + | {{inst|mn=LDRBT|col 1=LDRBT{cond} Rd, address |col 2=Load [[Byte]], User Mode Privilege |col 3 = Rd = ZeroExtend([address])}} | ||
| + | {{inst|mn=LDM |col 1=LDM{cond}{type} Rn[!], {reglist} |col 2= Load Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> Rd = [addr]<br> addr += {type} }} | ||
| + | {{inst|mn=LDM |col 1=LDM{cond}{type} Rn[!], {reglist, PC} |col 2= Load Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> Rd = [addr]<br> addr += {type}<br>R15 = [addr] }} | ||
| + | |||
| + | {{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span>}} | ||
| + | {{inst|mn=STR |col 1=STR{cond} Rd, address |col 2=Store Word |col 3 = [address] = Rd}} | ||
| + | {{inst|mn=STRT |col 1=STRT{cond} Rd, address |col 2=Store Word, User Mode Privilege |col 3 = [address] = Rd}} | ||
| + | {{inst|mn=STRB |col 1=STRB{cond} Rd, address |col 2=Store Byte |col 3 = [address][7:0] = Rd[7:0]}} | ||
| + | {{inst|mn=STRBT |col 1=STRBT{cond} Rd, address |col 2=Store Byte, User Mode Privilege |col 3 = [address][7:0] = Rd[7:0]}} | ||
| + | {{inst|mn=STM |col 1=STM{cond}{type} Rn[!], {reglist} |col 2= Store Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> [addr] = Rd<br> addr += {type} }} | ||
| + | {{inst|mn=STM |col 1=STM{cond}{type} Rn[!], {reglist}^ |col 2= Store Multiple, User Mode Privilege |col 3 = addr = Rn<br>for each Rd in {reglist}:<br> [addr] | ||
| + | = Rd<br> Rn += {type} }} | ||
| + | |||
| + | }} | ||
Revision as of 22:00, 26 June 2017
ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.
Overview
The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.
Registers
There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.
Instruction Listing
The ARMv1 is broken down into 2 classes of instruction:
| ARMv1 ISA | ||||
|---|---|---|---|---|
| Mnemonic | Syntax | Description | Action | |
| Load Instructions | ||||
| LDR | LDR{cond} Rd, address | Load Word | Rd = [address] | |
| LDRT | LDRT{cond} Rd, address | Load Word, User Mode Privilege | Rd = [address] | |
| LDRB | LDRB{cond} Rd, address | Load Byte | Rd = ZeroExtend([address]) | |
| LDRBT | LDRBT{cond} Rd, address | Load Byte, User Mode Privilege | Rd = ZeroExtend([address]) | |
| LDM | LDM{cond}{type} Rn[!], {reglist} | Load Multiple | addr = Rn for each Rd in {reglist}: Rd = [addr] addr += {type} | |
| LDM | LDM{cond}{type} Rn[!], {reglist, PC} | Load Multiple | addr = Rn for each Rd in {reglist}: Rd = [addr] addr += {type} R15 = [addr] | |
| Store Instructions | ||||
| STR | STR{cond} Rd, address | Store Word | [address] = Rd | |
| STRT | STRT{cond} Rd, address | Store Word, User Mode Privilege | [address] = Rd | |
| STRB | STRB{cond} Rd, address | Store Byte | [address][7:0] = Rd[7:0] | |
| STRBT | STRBT{cond} Rd, address | Store Byte, User Mode Privilege | [address][7:0] = Rd[7:0] | |
| STM | STM{cond}{type} Rn[!], {reglist} | Store Multiple | addr = Rn for each Rd in {reglist}: [addr] = Rd addr += {type} | |
| STM | STM{cond}{type} Rn[!], {reglist}^ | Store Multiple, User Mode Privilege | addr = Rn for each Rd in {reglist}: [addr] = Rd Rn += {type} | |