Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "loongson/godson 2/2d1"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
|||
| Line 51: | Line 51: | ||
| max memory = | | max memory = | ||
| − | + | ||
| power = 6 W | | power = 6 W | ||
| v core = | | v core = | ||
Revision as of 23:04, 23 June 2017
Template:mpu Godson-2D1 (龙芯2D1) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers.The Godson-2D1 operates at up to 800 MHz consuming up to 6 W. This chip was manufactured on STMicroelectronics' 0.13 µm process. This chip reached tapeout on January 6, 2005.
Loongson has claimed the Godson-2D has reached the performance level of 1.5 GHz PIV based on their SPECint2000 scores.
Cache
- Main article: GS464 § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||
|
|||||||||||||
Facts about "Godson-2D1 - Loongson"
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |