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Difference between revisions of "intel/xeon d/d-1548"
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| thread count        = 16
 
| thread count        = 16
 
| max cpus            = 1
 
| max cpus            = 1
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| max memory          = 128 GB
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| max memory          = 128 GiB
  
 
| electrical          = Yes
 
| electrical          = Yes

Revision as of 03:24, 23 June 2017

Template:mpu The Xeon D-1548 is a 64-bit octa-core x86-64 microserver SoC that was introduced by Intel in November of 2015. The D-1548 operates at 2 GHz with a turbo frequency of 2.6 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core)
L3$ 12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
8x1.5 MiB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max memory 128 GB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface Yes
KR interface Yes
KR4 interface No
KX interface Yes
KX4 interface No
10Base-T No
100Base-T No
1000Base-T Yes
10GBase-T Yes

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1548&oldid=46786"
Facts about "Xeon D-1548 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +