Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/am486/am486dx4-100sv16b"
(→Cache) |
m (Bot: corrected mem) |
||
| Line 45: | Line 45: | ||
| thread count = | | thread count = | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
Revision as of 02:17, 23 June 2017
Template:mpu Am486DX4-100SV16B was an Enhanced Am486 microprocessor introduced by AMD in 1997. This processor had a clock multiplier of 3 having a frequency of 100 MHz with a bus frequency of 33 MHz. This "Enhanced" Am486 includes some other features such as SMM, stop-clock control, and write-back cache. This model had larger L1 cache of 16 KB with Write-Back policy. This model has twice as much cache as the Am486DX4-100SV8B.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- Stop-clock control
- System Management Mode (SMM)
Packaging
| Part | Package |
|---|---|
| A80486DX4-100SV16B | CPGA-168 |
| S80486DX4-100SV16B | SQFP-208 |
See also
Facts about "Am486DX4-100SV16B - AMD"
| has feature | System Management Mode + |
| l1$ description | 4-way set associative + |
| l1$ size | 16 KiB (16,384 B, 0.0156 MiB) + |