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'''CN5734-1000 SSP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.  | '''CN5734-1000 SSP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.  | ||
Revision as of 23:23, 22 June 2017
Template:mpu CN5734-1000 SSP is a 64-bit hexa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
 
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 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller
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 Integrated Memory Controller 
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Expansions
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 Expansion Options 
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
 - 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
 - 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
 
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 Networking 
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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 Hardware Accelerators 
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Block diagram
Datasheet
Facts about "CN5734-1000 SSP  - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | CN5734-1000 SSP - Cavium#io + | 
| has ecc memory support | true + | 
| has hardware accelerators for cryptography | true + | 
| has hardware accelerators for data compression | true + | 
| has hardware accelerators for data decompression | true + | 
| has hardware accelerators for network quality of service processing | true + | 
| has hardware accelerators for tcp packet processing | true + | 
| has hardware raid 5 support | true + | 
| has hardware raid 6 support | true + | 
| l1$ size | 288 KiB (294,912 B, 0.281 MiB) + | 
| l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + | 
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 8 + | 
| supported memory type | DDR2-800 + |