From WikiChip
Difference between revisions of "intel/celeron/3965u"
Line 1: | Line 1: | ||
{{intel title|Celeron 3965U}} | {{intel title|Celeron 3965U}} | ||
{{mpu | {{mpu | ||
− | | name | + | |name=Celeron 3965U |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=3965U | |
− | | designer | + | |part number=FJ8067702739934 |
− | | manufacturer | + | |s-spec=SR34A |
− | | model number | + | |market=Mobile |
− | | part number | + | |first announced=January 3, 2017 |
− | + | |first launched=January 3, 2017 | |
− | | s-spec | + | |release price=$107.00 |
− | | market | + | |family=Celeron |
− | | first announced | + | |series=3900 |
− | | first launched | + | |locked=Yes |
− | + | |frequency=2,200 MHz | |
− | + | |bus type=OPI | |
− | | release price | + | |bus rate=4 GT/s |
− | + | |clock multiplier=22 | |
− | | family | + | |cpuid=306A9 |
− | | series | + | |isa=x86-64 |
− | | locked | + | |isa family=x86 |
− | | frequency | + | |microarch=Kaby Lake |
− | | bus type | + | |platform=Kaby Lake |
− | + | |core name=Kaby Lake U | |
− | | bus rate | + | |core family=6 |
− | + | |core model=58 | |
− | | clock multiplier | + | |core stepping=S0 |
− | | cpuid | + | |process=14 nm |
− | + | |technology=CMOS | |
− | | isa | + | |word size=64 bit |
− | | isa | + | |core count=2 |
− | | microarch | + | |thread count=2 |
− | | platform | + | |max cpus=1 |
− | + | |max memory=64 GiB | |
− | + | |v core min=0.25 V | |
− | | core name | + | |v core max=1.52 V |
− | | core family | + | |tdp=15 W |
− | | core model | + | |ctdp down=10 W |
− | | core stepping | + | |tjunc min=0 °C |
− | + | |tjunc max=100 °C | |
− | | process | + | |tstorage min=-25 °C |
− | + | |tstorage max=125 °C | |
− | | technology | + | |electrical=Yes |
− | + | |packaging=Yes | |
− | + | |package=FCBGA-1356 | |
− | + | |package type=FCBGA | |
− | | word size | + | |package pitch=0.65 mm |
− | | core count | + | |package size=42 mm x 24 mm |
− | | thread count | + | |socket=BGA-1356 |
− | | max cpus | + | |socket type=BGA |
− | | max memory | ||
− | |||
− | |||
− | | v core min | ||
− | | v core max | ||
− | | tdp | ||
− | |||
− | | ctdp down | ||
− | |||
− | |||
− | |||
− | | tjunc min | ||
− | | tjunc max | ||
− | |||
− | |||
− | | tstorage min | ||
− | | tstorage max | ||
− | | | ||
− | |||
− | |||
− | | packaging | ||
− | | package | ||
− | | package type | ||
− | | package pitch | ||
− | | package size | ||
− | | socket | ||
− | | socket type | ||
}} | }} | ||
'''Celeron 3965U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3965U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 2.2 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3965U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz. | '''Celeron 3965U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3965U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 2.2 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3965U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz. |
Revision as of 00:46, 21 June 2017
Template:mpu Celeron 3965U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3965U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 2.2 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3965U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.
This model has a configurable TDP-down of 10 W.
Cache
- Main article: Kaby Lake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||
|
Graphics
![]() |
Integrated Graphics Information
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, MVC, Stereo | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main, Main 10 | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | 3840x3840 | |||
VP8 | Unified | Unified | N/A | 0 | Unified | 1080p | |
VP9 | 0 | 2160p (4K) | 0, 2 | Unified | 2160p (4K) |
Features
[Edit/Modify Supported Features]
Facts about "Celeron 3965U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 3965U - Intel#io + |
device id | 0x5906 + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
integrated gpu | HD Graphics 610 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |