Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon gold/6152"
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|l3 cache=30.25 MiB | |l3 cache=30.25 MiB | ||
|l3 break=22x1.375 MiB | |l3 break=22x1.375 MiB | ||
| − | |l3 desc= | + | |l3 desc=11-way set associative |
|l3 policy=write-back | |l3 policy=write-back | ||
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Revision as of 08:47, 4 June 2017
Template:mpu Xeon Gold 6152 is a 64-bit x86 high-performance server docosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6152 operates at 2.1 GHz.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Xeon Gold 6152 - Intel"
| has ecc memory support | true + |
| l1$ size | 1,408 KiB (1,441,792 B, 1.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 704 KiB (720,896 B, 0.688 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 704 KiB (720,896 B, 0.688 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 30.25 MiB (30,976 KiB, 31,719,424 B, 0.0295 GiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| supported memory type | DDR4-2666 + |