From WikiChip
Difference between revisions of "intel/core m/m7-6y75"
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== Features == | == Features == | ||
− | {{ | + | {{x86 features |
− | | | + | |real=Yes |
− | | | + | |protected=Yes |
− | | | + | |smm=Yes |
− | | | + | |fpu=Yes |
− | | | + | |x8616=Yes |
− | | | + | |x8632=Yes |
− | | | + | |x8664=Yes |
− | | | + | |nx=Yes |
− | | | + | |mmx=Yes |
− | | | + | |emmx=Yes |
− | | | + | |sse=Yes |
− | | | + | |sse2=Yes |
− | | | + | |sse3=Yes |
− | | | + | |ssse3=Yes |
− | | | + | |sse41=Yes |
− | | | + | |sse42=Yes |
− | | | + | |sse4a=No |
− | | | + | |avx=No |
− | | | + | |avx2=No |
− | | | + | |avx512=No |
− | | | + | |abm=Yes |
− | | | + | |tbm=No |
− | | | + | |bmi1=Yes |
− | | | + | |bmi2=Yes |
− | | | + | |fma3=No |
− | | | + | |fma4=No |
− | | | + | |aes=Yes |
− | | | + | |rdrand=Yes |
− | | | + | |sha=No |
− | | | + | |xop=No |
− | | | + | |adx=Yes |
− | | | + | |clmul=Yes |
− | | | + | |f16c=Yes |
− | | | + | |tbt1=No |
− | | | + | |tbt2=No |
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=Yes | ||
+ | |fastmem=No | ||
+ | |isrt=Yes | ||
+ | |sba=No | ||
+ | |mwt=Yes | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=Yes | ||
+ | |securekey=Yes | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
}} | }} | ||
== Drivers == | == Drivers == | ||
* [[drivers url::https://downloadcenter.intel.com/product/94025|Drivers]] | * [[drivers url::https://downloadcenter.intel.com/product/94025|Drivers]] |
Revision as of 21:18, 3 June 2017
Template:mpu Core M7-6Y75 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.2 GHz with a max turbo frequency of 3.1 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M7-6Y75 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 1 GHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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[show] [Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities |
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Drivers
Facts about "Core m7-6Y75 - Intel"