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Difference between revisions of "intel/xeon e3/e3-1225 v5"
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|bandwidth schan=17.88 GiB/s
 
|bandwidth schan=17.88 GiB/s
 
|bandwidth dchan=35.76 GiB/s
 
|bandwidth dchan=35.76 GiB/s
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}}
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== Expansions ==
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{{expansions
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| pcie revision      = 3.0
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| pcie lanes        = 16
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| pcie config        = 1x16
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| pcie config 2      = 2x8
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| pcie config 3      = 1x8+2x4
 
}}
 
}}
  
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}}
 
}}
 
{{skylake hardware accelerated video table|col=1}}
 
{{skylake hardware accelerated video table|col=1}}
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== Expansions ==
 
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{{mpu expansions
 
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| pcie revision      = 3.0
 
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| pcie lanes        = 16
 
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| pcie config        = 1x16
 
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| pcie config 1      = 2x8
 
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| pcie config 2      = 1x8+2x4
 
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| usb revision      =
 
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| usb revision 2    =
 
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| usb revision N    =
 
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| usb ports          =
 
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| sata ports        =
 
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| integrated lan    =
 
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| uart              =
 
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}}
 
  
 
== Features ==  
 
== Features ==  

Revision as of 09:57, 3 June 2017

Template:mpu Xeon E3-1225 V5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.3 GHz with turbo boost of 3.7 GHz. The E3-1225 V5 has a TDP of 25 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has the HD Graphics P530 IGP.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics P530
DesignerIntelDevice ID0x191D
Execution Units24Max Displays3
Max Memory1.7 GiB
1,740.8 MiB
1,782,579.2 KiB
1,825,361,100.8 B
Frequency400 MHz
0.4 GHz
400,000 KHz
Burst Frequency1,150 MHz
1.15 GHz
1,150,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @30 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1225_v5&oldid=43990"
Facts about "Xeon E3-1225 v5 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E3-1225 v5 - Intel#io +
device id0x191D +
has ecc memory supporttrue +
integrated gpuHD Graphics P530 +
integrated gpu base frequency400 MHz (0.4 GHz, 400,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units24 +
integrated gpu max frequency1,150 MHz (1.15 GHz, 1,150,000 KHz) +
integrated gpu max memory1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max pcie lanes16 +
supported memory typeDDR3L-1600 + and DDR4-2133 +