Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon e3/e3-1268l v5"
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== Graphics == | == Graphics == | ||
| − | {{integrated | + | {{integrated graphics |
| − | | gpu = | + | | gpu = HD Graphics P530 |
| device id = 0x191D | | device id = 0x191D | ||
| + | | designer = Intel | ||
| execution units = 24 | | execution units = 24 | ||
| − | | displays | + | | max displays = 3 |
| + | | max memory = 1.7 GiB | ||
| frequency = 350 MHz | | frequency = 350 MHz | ||
| − | | max frequency = 1 | + | | max frequency = 1,000 MHz |
| − | |||
| output crt = | | output crt = | ||
| Line 133: | Line 134: | ||
| output dvi = Yes | | output dvi = Yes | ||
| − | | directx ver | + | | directx ver = 12 |
| − | | opengl ver | + | | opengl ver = 4.4 |
| − | | opencl ver | + | | opencl ver = 2.0 |
| − | | | + | | hdmi ver = 1.4a |
| − | | | + | | dp ver = 1.2 |
| − | | | + | | edp ver = 1.3 |
| − | | | + | | max res hdmi = 4096x2304 |
| − | | | + | | max res hdmi freq = 30 Hz |
| − | | dp | + | | max res dp = 4096x2304 |
| − | | edp | + | | max res dp freq = 60 Hz |
| + | | max res edp = 4096x2304 | ||
| + | | max res edp freq = 60 Hz | ||
| + | | max res vga = | ||
| + | | max res vga freq = | ||
| − | | | + | | features = Yes |
| − | + | | intel quick sync = Yes | |
| − | + | | intel intru 3d = Yes | |
| − | + | | intel insider = | |
| − | + | | intel widi = | |
| − | + | | intel fdi = | |
| − | + | | intel clear video = Yes | |
| − | + | | intel clear video hd = Yes | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | | intel quick sync | ||
| − | | intel intru 3d | ||
| − | | intel insider | ||
| − | | intel widi | ||
| − | | intel fdi | ||
| − | | intel clear video | ||
}} | }} | ||
| + | {{skylake hardware accelerated video table|col=1}} | ||
== Expansions == | == Expansions == | ||
Revision as of 09:39, 3 June 2017
Template:mpu Xeon E3-1268L V5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2.4 GHz with turbo boost of 3.4 GHz. The E3-1268L V5 is an ultra low power chip with a TDP of 35 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has the HD Graphics P530 IGP underclocked to 350 MHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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| [Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
| MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
| JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
| HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
| VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
| VP9 | ✘ | 0 | Unified | 2160p (4K) | |||
Expansions
Features
Facts about "Xeon E3-1268L v5 - Intel"
| device id | 0x191D + |
| has ecc memory support | true + |
| integrated gpu | HD Graphics P530 + |
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 24 + |
| integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
| integrated gpu max memory | 1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |