Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e3/e3-1225 v5"
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| socket type = LGA | | socket type = LGA | ||
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| − | + | '''Xeon E3-1225 V5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.3 GHz with turbo boost of 3.7 GHz. The E3-1225 V5 has a TDP of 25 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has the {{intel|HD Graphics P530}} [[integrated graphics processor|IGP]]. | |
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache=256 KiB | ||
|l1i cache=128 KiB | |l1i cache=128 KiB | ||
|l1i break=4x32 KiB | |l1i break=4x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |||
|l1d cache=128 KiB | |l1d cache=128 KiB | ||
|l1d break=4x32 KiB | |l1d break=4x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
|l2 break=4x256 KiB | |l2 break=4x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=8 MiB | |l3 cache=8 MiB | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
| + | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 17:39, 2 June 2017
Template:mpu Xeon E3-1225 V5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.3 GHz with turbo boost of 3.7 GHz. The E3-1225 V5 has a TDP of 25 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has the HD Graphics P530 IGP.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
| Integrated Graphic Information | |
| GPU | Intel HD Graphics P530 |
| Device ID | 0x191D |
| Execution Units | 24 |
| Displays | 3 |
| Frequency | 400 MHz 0.4 GHz
400,000 KHz |
| Max frequency | 1.15 GHz 1,150 MHz
1,150,000 KHz |
| Max memory | 1.7 GB "GB" is not declared as a valid unit of measurement for this property.
|
| Output | DisplayPort, Embedded DisplayPort, HDMI, DVI |
| DirectX | 12.1 |
| OpenGL | 4.4 |
| OpenCL | 2.0 |
| HDMI | 1.4 |
| DP | 1.2 |
| eDP | 1.3 |
| Max HDMI Res | 4096x2160 @24 Hz |
| Max DP Res | 4096x2304 @60 Hz |
| Max eDP Res | 4096x2304 @60 Hz |
| Intel Quick Sync Video | |
| Intel InTru 3D | |
| Intel Insider | |
| Intel WiDi (Wireless Display) | |
| Intel Clear Video | |
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-1333, DDR3L-1600, DDR3L-RS1333, DDR3L-RS1600, DDR4-1866, DDR4-2133, DDR4-RS1866, DDR4-RS2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max bandwidth | 34.1 GB/s |
| Max memory | 64 GB |
Expansions
Features
Facts about "Xeon E3-1225 v5 - Intel"
| device id | 0x191D + |
| has feature | integrated gpu + |
| integrated gpu | Intel HD Graphics P530 + |
| integrated gpu base frequency | 400 MHz (0.4 GHz, 400,000 KHz) + |
| integrated gpu max frequency | 1,150 MHz (1.15 GHz, 1,150,000 KHz) + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |