From WikiChip
Difference between revisions of "intel/xeon e3/e3-1240 v5"
< intel

(→‎Cache)
Line 16: Line 16:
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
 +
| release price      = $282
  
 
| family              = Xeon E3
 
| family              = Xeon E3
Line 29: Line 30:
 
| bus speed          =  
 
| bus speed          =  
 
| bus rate            = 8 GT/s
 
| bus rate            = 8 GT/s
−
| clock multiplier    =  
+
| clock multiplier    = 35
 
| s-spec              = SR2CM
 
| s-spec              = SR2CM
 
| s-spec 2            = SR2LD
 
| s-spec 2            = SR2LD
Line 36: Line 37:
 
| cpuid              = 506E3
 
| cpuid              = 506E3
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Skylake
 
| microarch          = Skylake
 
| platform            = Greenlow
 
| platform            = Greenlow
Line 46: Line 49:
 
| transistors        =  
 
| transistors        =  
 
| technology          = CMOS
 
| technology          = CMOS
−
| die size           =  
+
| die area           = 122 mm²
 
| word size          = 64 bit
 
| word size          = 64 bit
 
| core count          = 4
 
| core count          = 4
 
| thread count        = 8
 
| thread count        = 8
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 64 GB
+
| max memory          = 64 GiB
  
 
| electrical          = Yes
 
| electrical          = Yes
Line 58: Line 61:
 
| sdp                =  
 
| sdp                =  
 
| tdp                = 80 W
 
| tdp                = 80 W
−
| ctdp down           =  
+
| tjunc min           = 0 °C
−
| ctdp down frequency =
+
| tjunc max          = 100 °C
−
| ctdp up            =
+
| tcase min          =  
−
| ctdp up frequency  =
+
| tcase max          =  
−
| temp max           = 100 °C
+
| tstorage min        = -25 °C
−
| temp min           = 0 °C
+
| tstorage max       = 125 °C
 +
| tambient min       =
 +
| tambient max        =  
  
 
| packaging          = Yes
 
| packaging          = Yes

Revision as of 17:17, 2 June 2017

Template:mpu The Xeon E3-1240 V5 is an entry-level workstations and servers 64-bit x86 quad-core microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no integrated graphics processor.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 4-way set associative (per core)
L3$ 8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
4x2 MiB

Graphics

This chip has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR3L-RS1333, DDR3L-RS1600, DDR4-1866, DDR4-2133, DDR4-RS1866, DDR4-RS2133
Controllers 1
Channels 2
ECC Support Yes
Max bandwidth 34.1 GB/s
Max memory 64 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1240_v5&oldid=43935"
Facts about "Xeon E3-1240 v5 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +