From WikiChip
Difference between revisions of "intel/core i9/i9-7960x"
< intel‎ | core i9

Line 89: Line 89:
  
 
{{unknown features}}
 
{{unknown features}}
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 +
{{cache size
 +
|l1 cache=1 MiB
 +
|l1i cache=512 KiB
 +
|l1i break=16x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=512 KiB
 +
|l1d break=16x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=16 MiB
 +
|l2 break=16x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=22 MiB
 +
|l3 break=16x1.375 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 21:24, 31 May 2017

Template:mpu Core i9-7960X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by Intel in mid-2017. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's 14 nm process. The i7-7960X operates at ? GHz with a TDP of 160 W and a Turbo Boost frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  16x1 MiB16-way set associativewrite-back
L3$22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
  16x1.375 MiB16-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i9/i9-7960x&oldid=43703"
Facts about "Core i9-7960X - Intel"
RDF feed
l1$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description16-way set associative +
l3$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +