From WikiChip
Difference between revisions of "intel/core i9/i9-7960x"
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+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1 MiB | ||
+ | |l1i cache=512 KiB | ||
+ | |l1i break=16x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=512 KiB | ||
+ | |l1d break=16x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=16 MiB | ||
+ | |l2 break=16x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=22 MiB | ||
+ | |l3 break=16x1.375 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} |
Revision as of 20:24, 31 May 2017
Template:mpu Core i9-7960X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by Intel in mid-2017. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's 14 nm process. The i7-7960X operates at ? GHz with a TDP of 160 W and a Turbo Boost frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i9-7960X - Intel"
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |