Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:nodes comp"
| (6 intermediate revisions by one other user not shown) | |||
| Line 8: | Line 8: | ||
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 fab|}}} }}<!-- | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 fab|}}} }}<!-- | ||
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 fab|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 fab|}}} }}<!-- | ||
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fab|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fab|}}} }}<!-- |
| + | -->{{#if: {{{process 7 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 7 fab|}}} }}<!-- | ||
| + | -->{{#if: {{{process 8 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 8 fab|}}} }}<!-- | ||
| + | -->{{#if: {{{process 9 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 9 fab|}}} }}<!-- | ||
| + | -->{{#if: {{{process 10 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 10 fab|}}} }}<!-- | ||
| + | -->{{#if: {{{process 11 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 11 fab|}}} }}<!-- | ||
| + | -->{{#if: {{{process 12 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 12 fab|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 name|}}}<!-- | | colspan="2" | {{{process 1 name|}}}<!-- | ||
| Line 15: | Line 21: | ||
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 name|}}} }}<!-- | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 name|}}} }}<!-- | ||
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 name|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 name|}}} }}<!-- | ||
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 name|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 name|}}} }}<!-- |
| + | -->{{#if: {{{process 7 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 7 name|}}} }}<!-- | ||
| + | -->{{#if: {{{process 8 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 8 name|}}} }}<!-- | ||
| + | -->{{#if: {{{process 9 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 9 name|}}} }}<!-- | ||
| + | -->{{#if: {{{process 10 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 10 name|}}} }}<!-- | ||
| + | -->{{#if: {{{process 11 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 11 name|}}} }}<!-- | ||
| + | -->{{#if: {{{process 12 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 12 name|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 date|}}}<!-- | | colspan="2" | {{{process 1 date|}}}<!-- | ||
| Line 22: | Line 34: | ||
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 date|}}} }}<!-- | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 date|}}} }}<!-- | ||
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 date|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 date|}}} }}<!-- | ||
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 date|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 date|}}} }}<!-- |
| + | -->{{#if: {{{process 7 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 7 date|}}} }}<!-- | ||
| + | -->{{#if: {{{process 8 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 8 date|}}} }}<!-- | ||
| + | -->{{#if: {{{process 9 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 9 date|}}} }}<!-- | ||
| + | -->{{#if: {{{process 10 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 10 date|}}} }}<!-- | ||
| + | -->{{#if: {{{process 11 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 11 date|}}} }}<!-- | ||
| + | -->{{#if: {{{process 12 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 12 date|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 lith|}}}<!-- | | colspan="2" | {{{process 1 lith|}}}<!-- | ||
| Line 29: | Line 47: | ||
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 lith|}}} }}<!-- | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 lith|}}} }}<!-- | ||
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 lith|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 lith|}}} }}<!-- | ||
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 lith|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 lith|}}} }}<!-- |
| + | -->{{#if: {{{process 7 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 7 lith|}}} }}<!-- | ||
| + | -->{{#if: {{{process 8 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 8 lith|}}} }}<!-- | ||
| + | -->{{#if: {{{process 9 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 9 lith|}}} }}<!-- | ||
| + | -->{{#if: {{{process 10 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 10 lith|}}} }}<!-- | ||
| + | -->{{#if: {{{process 11 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 11 lith|}}} }}<!-- | ||
| + | -->{{#if: {{{process 12 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 12 lith|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 immersion|}}}<!-- | | colspan="2" | {{{process 1 immersion|}}}<!-- | ||
| Line 36: | Line 60: | ||
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 immersion|}}} }}<!-- | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 immersion|}}} }}<!-- | ||
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 immersion|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 immersion|}}} }}<!-- | ||
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 immersion|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 immersion|}}} }}<!-- |
| + | -->{{#if: {{{process 7 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 7 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 8 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 8 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 9 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 9 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 10 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 10 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 11 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 11 immersion|}}} }}<!-- | ||
| + | -->{{#if: {{{process 12 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 12 immersion|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="2" | {{{process 1 exposure|}}}<!-- | | colspan="2" | {{{process 1 exposure|}}}<!-- | ||
| Line 88: | Line 118: | ||
|- | |- | ||
| {{{process 1 gate len|}}} || {{#ifeq: {{{process 1 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 1 gate len Δ|}}} }}<!-- | | {{{process 1 gate len|}}} || {{#ifeq: {{{process 1 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 1 gate len Δ|}}} }}<!-- | ||
| − | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{#ifeq: {{{process 2 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 2 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 2 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{#ifeq: {{{process 3 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 3 gate len Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 3 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 3 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{#ifeq: {{{process 4 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 4 gate len Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 4 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 4 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{#ifeq: {{{process 5 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 5 gate len Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 5 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 5 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{#ifeq: {{{process 6 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 6 gate len Δ|}}} }} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 6 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 6 gate len Δ|}}} }} }} |
|- | |- | ||
| {{{process 1 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 1 cpp Δ|}}} }}<!-- | | {{{process 1 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 1 cpp Δ|}}} }}<!-- | ||
Latest revision as of 18:11, 29 May 2017
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Metal Layers | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Value | |
|---|---|