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Difference between revisions of "intel/xeon platinum/8176"
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|l2 cache=28 MiB | |l2 cache=28 MiB | ||
|l2 break=28x1 MiB | |l2 break=28x1 MiB | ||
− | |l2 desc= | + | |l2 desc=16-way set associative |
|l2 policy=write-back | |l2 policy=write-back | ||
|l3 cache=38.5 MiB | |l3 cache=38.5 MiB |
Revision as of 13:39, 26 May 2017
Template:mpu Xeon Platinum 8176 is a 64-bit x86 high-performance server octacosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 8176 operates at 2.1 GHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Xeon Platinum 8176 - Intel"
has ecc memory support | true + |
l1$ size | 1,792 KiB (1,835,008 B, 1.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
supported memory type | DDR4-2666 + |