From WikiChip
Difference between revisions of "WikiChip:sandbox"

(→‎comptable)
(→‎comptable)
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== comptable ==
 
== comptable ==
 
<timeline>
 
<timeline>
−
ImageSize  = width:1000 height:300
+
ImageSize  = width:1000 height:400
−
PlotArea  = left:20 right:10 top:10 bottom:25 #left:0 right:0 bottom:20 top:0
+
PlotArea  = left:150 right:10 top:10 bottom:25 #left:0 right:0 bottom:20 top:0
  
 
DateFormat = mm/dd/yyyy
 
DateFormat = mm/dd/yyyy
Line 114: Line 114:
 
   id:c_core1 value:rgb(0.47,0.83,0.91)
 
   id:c_core1 value:rgb(0.47,0.83,0.91)
 
   id:c_core2 value:rgb(0.97,0.90,0.72)
 
   id:c_core2 value:rgb(0.97,0.90,0.72)
−
   id:c_core3 value:rgb(0.98,0.73,0.87)
+
   id:c_core3 value:rgb(0.68,1,0.91)
−
   id:c_core4 value:rgb(0.78,0.82,0.96)
+
   id:c_core4 value:rgb(0.98,0.73,0.87)
−
   id:c_core5 value:rgb(0.84,0.97,0.96)
+
   id:c_core5 value:rgb(0.78,0.82,0.96)
−
   id:c_core6 value:rgb(0.95,0.83,1)
+
   id:c_core6 value:rgb(0.84,0.97,0.96)
−
   id:c_core7 value:rgb(0.89,0.95,0.87)
+
   id:c_core7 value:rgb(0.95,0.83,1)
−
   id:c_core8 value:rgb(0.68,1,0.91)
+
   id:c_core8 value:rgb(0.89,0.95,0.87)
 
   id:c_core9 value:rgb(0.78,0.93,1)
 
   id:c_core9 value:rgb(0.78,0.93,1)
  
Line 160: Line 160:
 
   color:c_core2
 
   color:c_core2
 
   bar:core2
 
   bar:core2
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y2"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake U"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U2"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake U"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake U"
 
   color:c_core3
 
   color:c_core3
 
   bar:core3
 
   bar:core3
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y3"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake H"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U3"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake H"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake H"
 
   color:c_core4
 
   color:c_core4
 
   bar:core4
 
   bar:core4
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y4"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake S"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U4"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake S"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake S"
 
   color:c_core5
 
   color:c_core5
 
   bar:core5
 
   bar:core5
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y5"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake DT"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U5"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake DT"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake DT"
 
   color:c_core6
 
   color:c_core6
 
   bar:core6
 
   bar:core6
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y6"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake X"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U6"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake X"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake X"
 
   color:c_core7
 
   color:c_core7
 
   bar:core7
 
   bar:core7
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y7"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake E"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U7"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake E"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake E"
 
   color:c_core8
 
   color:c_core8
 
   bar:core8
 
   bar:core8
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y8"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EP"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U8"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EP"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EP"
 
   color:c_core9
 
   color:c_core9
 
   bar:core9
 
   bar:core9
−
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y9"
+
     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EX"
−
     anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U9"
+
     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EX"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EX"
 
</timeline>
 
</timeline>
  

Revision as of 02:18, 13 May 2017

Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.


 
ssssssssssss
DATA
BUS
I/O		D00116CM-RAM0X
D10215CM-RAM1X
D20314CM-RAM2X
 D30413CM-RAM3X
Vss0512VddX
CLOCK
PHASE 1/2		Ø10611CM-ROMX
Ø20710TESTX
SYNC0809RESETX
123456789


Sitemap font awesome.svgCache Info
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes.
[Edit Values]
L1$128 KiB
L1I$64 KiB1x64 KiB2-way set associativewrite-back
L1D$64 KiB1x64 KiB2-way set associativewrite-back
L2$128 KiB
L2I$64 KiB1x64 KiB2-way set associativewrite-back
L2D$64 KiB1x64 KiB2-way set associativewrite-back
L3$128 KiB
L3I$64 KiB1x64 KiB2-way set associativewrite-back
L3D$64 KiB1x64 KiB2-way set associativewrite-back
L4$128 KiB
L4I$64 KiB1x64 KiB2-way set associativewrite-back
L4D$64 KiB1x64 KiB2-way set associativewrite-back
Off-package cache support
Mobo512 KiB
1x64 KiB2-way set associativewrite-back


wireless test

Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11-1997Yes
802.11aYes
802.11bYes
802.11gYes
802.11nYes
802.11acYes
802.11adYes
Cellular
2G
GSM Yes
GPRS Yes
EDGE Yes
cdmaOne
IS-95AYes
IS-95BYes
3G
UMTS
WCDMAYes
HSDPAYes7.2 Mbps
HSUPAYes5.76 Mbps
CDMA2000
1XYes
1xEV-DOYes
1X AdvancedYes
Satellite

mpu

AMD-X5-133ADW
KL AMD 5x86.jpg
General Info
DesignerAMD
ManufacturerAMD
Model NumberAMD-X5-133ADW
Part NumberAMD-X5-133ADW,
AMD-X5-133ADW,
AMD-X5-133ADW
MarketDesktop
MarketDesktop
ecd9c6

comptable

intel/microarchitectures/tigerlakeintel/microarchitectures/icelakeintel/microarchitectures/cannonlakeintel/microarchitectures/coffee lakeintel/microarchitectures/kaby lakeintel/microarchitectures/skylake


Tabl test

Microarchitecture template

Microarchitectures
Paradigms
Single-CycleMulti-CyclePipelining
SuperpipeliningSuperscalarOOoE
Pipeline
Prefetching (instruction prefetch)
Fetching (instruction fetch)
Decoding (instruction decode)
micro-operationmacro-operationinternal operation
µOP cacheµOP fusion 
Out-of-Order
OOoESpeculativeFlushing
Components
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