Semiconductor & Computer Engineering
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Difference between revisions of "loongson/godson 2/2b"
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'''Godson-2B''' ('''龙芯2B''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late [[2003]], the Godson-2B operates at up to 250 MHz consuming up to 3 W. This chip was manufactured on [[SMICS]]' [[0.18 µm process]] and is known as China's first {{arch|64}} microprocessor. | '''Godson-2B''' ('''龙芯2B''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late [[2003]], the Godson-2B operates at up to 250 MHz consuming up to 3 W. This chip was manufactured on [[SMICS]]' [[0.18 µm process]] and is known as China's first {{arch|64}} microprocessor. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache=64 KiB | ||
| + | |l1i cache=32 KiB | ||
| + | |l1i break=1x32 KiB | ||
| + | |l1i desc= | ||
| + | |l1d cache=32 KiB | ||
| + | |l1d break=1x32 KiB | ||
| + | |l1d desc= | ||
| + | |l1d policy= | ||
| + | }} | ||
Revision as of 16:08, 19 March 2017
Template:mpu Godson-2B (龙芯2B) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late 2003, the Godson-2B operates at up to 250 MHz consuming up to 3 W. This chip was manufactured on SMICS' 0.18 µm process and is known as China's first 64-bit microprocessor.
Cache
- Main article: GS464 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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