Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i3/i3-7310t"
| Line 14: | Line 14: | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | s-spec = | ||
| + | | s-spec 2 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = | | first announced = | ||
| Line 21: | Line 23: | ||
| family = Core i3 | | family = Core i3 | ||
| − | | series = | + | | series = i3-7300 |
| locked = Yes | | locked = Yes | ||
| frequency = 3,400 MHz | | frequency = 3,400 MHz | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| bus type = DMI 3.0 | | bus type = DMI 3.0 | ||
| bus speed = | | bus speed = | ||
| bus rate = 8 GT/s | | bus rate = 8 GT/s | ||
| clock multiplier = 34 | | clock multiplier = 34 | ||
| − | |||
| − | |||
| − | |||
| cpuid = | | cpuid = | ||
| Line 45: | Line 35: | ||
| isa = x86-64 | | isa = x86-64 | ||
| microarch = Kaby Lake | | microarch = Kaby Lake | ||
| − | | platform = | + | | platform = Kaby Lake |
| − | | chipset = | + | | chipset = Sunrise Point |
| + | | chipset 2 = Union Point | ||
| core name = Kaby Lake S | | core name = Kaby Lake S | ||
| − | | core family = | + | | core family = 6 |
| − | | core model = | + | | core model = 158 |
| core stepping = | | core stepping = | ||
| + | | core stepping 2 = | ||
| process = 14 nm | | process = 14 nm | ||
| transistors = | | transistors = | ||
| Line 57: | Line 49: | ||
| die width = | | die width = | ||
| die length = | | die length = | ||
| − | | word size = | + | | word size = 64 bit |
| core count = 2 | | core count = 2 | ||
| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 64 | + | | max memory = 64 GiB |
| − | |||
| electrical = Yes | | electrical = Yes | ||
| − | + | | v core min = 0.55 V | |
| − | | v core | + | | v core max = 1.52 V |
| − | | v core | ||
| − | |||
| − | |||
| sdp = | | sdp = | ||
| tdp = 35 W | | tdp = 35 W | ||
| − | | | + | | tdp typical = |
| − | | | + | | ctdp down = |
| − | | tjunc min = | + | | ctdp down frequency = |
| − | | tjunc max = | + | | tjunc min = 0 °C |
| − | | tcase min = | + | | tjunc max = ? °C |
| − | | tcase max = | + | | tcase min = |
| − | | tstorage min = | + | | tcase max = |
| − | | | + | | tstorage min = -25 °C |
| + | | tstorage max = 125 °C | ||
| + | | tambient min = | ||
| + | | tambient max = | ||
| − | + | | package module 1 = {{packages/intel/lga-1151}} | |
| − | | package | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
| − | + | '''Core i3-7310T''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14 nm+ process]]. This processor, which has a base frequency of 3.4 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400. The i3-7310T incorporates Intel's {{intel|HD Graphics 630}} [[IGP]] operating at 350 MHz with burst frequency of 1.10 GHz. | |
| Line 95: | Line 80: | ||
== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}} |
| − | {{cache | + | {{cache size |
| + | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=2x32 KiB | |l1i break=2x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |l1i | + | |l1i policy=write-back |
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=2x32 KiB | |l1d break=2x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=512 KiB | |l2 cache=512 KiB | ||
|l2 break=2x256 KiB | |l2 break=2x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
| − | |l3 cache= | + | |l3 cache=4 MiB |
| − | |l3 desc= | + | |l3 break=2x2 MiB |
| + | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 21:26, 11 January 2017
Template:mpu Core i3-7310T is a 64-bit dual-core low-end performance x86 desktop microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 3.4 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400. The i3-7310T incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with burst frequency of 1.10 GHz.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i3-7310T - Intel"
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |