From WikiChip
Difference between revisions of "intel/xeon e3/e3-1535m v6"
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| pcie config 2 = 2x8 | | pcie config 2 = 2x8 | ||
| pcie config 3 = 1x8+2x4 | | pcie config 3 = 1x8+2x4 | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | {{integrated graphics | ||
+ | | gpu = HD Graphics P630 | ||
+ | | device id = 0x591D | ||
+ | | designer = Intel | ||
+ | | execution units = 24 | ||
+ | | max displays = 3 | ||
+ | | max memory = 64 GiB | ||
+ | | frequency = 350 MHz | ||
+ | | max frequency = 1,000 MHz | ||
+ | |||
+ | | output crt = | ||
+ | | output sdvo = | ||
+ | | output dsi = | ||
+ | | output edp = Yes | ||
+ | | output dp = Yes | ||
+ | | output hdmi = Yes | ||
+ | | output vga = | ||
+ | | output dvi = Yes | ||
+ | |||
+ | | directx ver = 12 | ||
+ | | opengl ver = 4.4 | ||
+ | | opencl ver = 2.0 | ||
+ | | hdmi ver = 1.4a | ||
+ | | dp ver = 1.2 | ||
+ | | edp ver = 1.3 | ||
+ | | max res hdmi = 4096x2304 | ||
+ | | max res hdmi freq = 30 Hz | ||
+ | | max res dp = 4096x2304 | ||
+ | | max res dp freq = 60 Hz | ||
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | |||
+ | | features = Yes | ||
+ | | intel quick sync = Yes | ||
+ | | intel intru 3d = Yes | ||
+ | | intel insider = | ||
+ | | intel widi = | ||
+ | | intel fdi = | ||
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = Yes | ||
}} | }} |
Revision as of 20:28, 8 January 2017
Template:mpu Xeon E3-1535M v6 is a 64-bit quad-core entry-level workstations and dense servers x86 microprocessor introduced by Intel in 2017. This processor, which is based on the Kaby Lake microarchitecture, is manufactured on Intel's improved 14nm+ process. The E3-1535M v6 operates at 3.1 GHz with a TDP of 45 W and with a Turbo Boost frequency of 4.2 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel ECC DDR4-2400 memory and incorporates Intel's HD Graphics P630 IGP operating at 350 MHz with a burst frequency of 1.1 GHz.
Contents
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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Facts about "Xeon E3-1535M v6 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1535M v6 - Intel#io + |
device id | 0x591D + |
has ecc memory support | true + |
integrated gpu | HD Graphics P630 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3L-1600 +, LPDDR3-2133 + and DDR4-2400 + |