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Difference between revisions of "intel/core i7/i7-7600u"
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'''Core i7-7600U''' is a {{arch|64}} [[dual-core]] high-end performance [[x86]] mobile microprocessor introduced by [[Intel]] in early [[2017]]. This processor, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is manufactured on Intel's improved [[14 nm process|14nm+ process]]. The i7-7600U operates at 2.8 GHz with a TDP of 15 W and with a {{intel|Turbo Boost}} frequency of 3.9 GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphics 620}} [[IGP]] operating at 300 MHz with a burst frequency of 1.15 GHz. | '''Core i7-7600U''' is a {{arch|64}} [[dual-core]] high-end performance [[x86]] mobile microprocessor introduced by [[Intel]] in early [[2017]]. This processor, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is manufactured on Intel's improved [[14 nm process|14nm+ process]]. The i7-7600U operates at 2.8 GHz with a TDP of 15 W and with a {{intel|Turbo Boost}} frequency of 3.9 GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphics 620}} [[IGP]] operating at 300 MHz with a burst frequency of 1.15 GHz. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1i policy=write-back | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=512 KiB | ||
+ | |l2 break=2x256 KiB | ||
+ | |l2 desc=4-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=4 MiB | ||
+ | |l3 break=2x2 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} |
Revision as of 22:51, 6 January 2017
Template:mpu Core i7-7600U is a 64-bit dual-core high-end performance x86 mobile microprocessor introduced by Intel in early 2017. This processor, which is based on the Kaby Lake microarchitecture, is manufactured on Intel's improved 14nm+ process. The i7-7600U operates at 2.8 GHz with a TDP of 15 W and with a Turbo Boost frequency of 3.9 GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's HD Graphics 620 IGP operating at 300 MHz with a burst frequency of 1.15 GHz.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i7-7600U - Intel"
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |