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Difference between revisions of "intel/core i5/i5-7y54"
< intel‎ | core i5

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|bandwidth schan=13.9 GiB/s
 
|bandwidth schan=13.9 GiB/s
 
|bandwidth dchan=27.81 GiB/s
 
|bandwidth dchan=27.81 GiB/s
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}}
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== Expansions ==
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{{expansions
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| pcie revision      = 3.0
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| pcie lanes        = 10
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| pcie config        = 1x4
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| pcie config 2      = 2x2
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| pcie config 3      = 1x2+2x1
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| pcie config 4      = 4x1
 
}}
 
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| intel fdi          =  
 
| intel fdi          =  
 
| intel clear video  = Yes
 
| intel clear video  = Yes
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== Expansions ==
 
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{{mpu expansions
 
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| pcie revision      = 3.0
 
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| pcie lanes        = 10
 
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| pcie config        = 1x4
 
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| pcie config 1      = 2x2
 
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| pcie config 2      = 1x2+2x1
 
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| pcie config 3      = 4x16x1
 
 
}}
 
}}
  

Revision as of 17:44, 6 January 2017

Template:mpu Core i5-7Y54 is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7Y54 operates at 1.2 GHz with a TDP of 4.5 W supporting a Turbo Boost frequency of 3.2 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's HD Graphics 615 IGP operating at 300 MHz with a burst frequency of 950 MHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB12-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, LPDDR3-1866
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth27.81 GiB/s
28,477.44 MiB/s
29.861 GB/s
29,860.76 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.9 GiB/s
Double 27.81 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes10
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

Integrated Graphic Information
GPU Intel HD Graphics 615
Device ID 0x591E
Execution Units 24
Displays 3
Frequency 300 MHz
0.3 GHz
300,000 KHz
Max frequency 950 MHz
0.95 GHz
950,000 KHz
Max memory 16 GB
"GB" is not declared as a valid unit of measurement for this property.
Output DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX 12
OpenGL 4.4
OpenCL 2.0
HDMI 1.4a
DP 1.2
eDP 1.3
Max HDMI Res 4096x2304 @24 Hz
Max DP Res 3840x2160 @60 Hz, 2880x1800 @60 Hz
Max eDP Res 3840x2160 @60 Hz, 3840x2160 @60 Hz
Intel Quick Sync Video
Intel InTru 3D
Intel Insider
Intel WiDi (Wireless Display)
Intel Clear Video

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-7y54&oldid=33109"
Facts about "Core i5-7Y54 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i5-7Y54 - Intel#io +
device id0x591E +
has ecc memory supportfalse +
has featureintegrated gpu +
integrated gpuIntel HD Graphics 615 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency950 MHz (0.95 GHz, 950,000 KHz) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
max memory bandwidth27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels2 +
max pcie lanes10 +
supported memory typeDDR3L-1600 + and LPDDR3-1866 +