Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i5/i5-7400t"
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== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}} |
| − | {{cache | + | {{cache size |
| + | |l1 cache=256 KiB | ||
|l1i cache=128 KiB | |l1i cache=128 KiB | ||
|l1i break=4x32 KiB | |l1i break=4x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |l1i | + | |l1i policy=write-back |
|l1d cache=128 KiB | |l1d cache=128 KiB | ||
|l1d break=4x32 KiB | |l1d break=4x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
|l2 break=4x256 KiB | |l2 break=4x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=6 MiB | |l3 cache=6 MiB | ||
| − | |l3 desc= | + | |l3 break=4x1.5 MiB |
| + | |l3 desc=12-way set associative | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 05:53, 6 January 2017
Template:mpu Core i5-7400T is a 64-bit quad-core mid-range performance x86 desktop microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7400T operates at 2.4 GHz with a TDP of 35 W supporting a Turbo Boost frequency of 3 GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with a burst frequency of 1 GHz.
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
| Integrated Graphic Information | |
| GPU | Intel HD Graphics 630 |
| Execution Units | 24 |
| Displays | 3 |
| Frequency | ? MHz "? MHz" is not a number.
|
| Max frequency | ? GHz "? GHz" is not a number.
|
| Max memory | 64 GB "GB" is not declared as a valid unit of measurement for this property.
|
| Output | DisplayPort, Embedded DisplayPort, HDMI, DVI |
| DirectX | 12.1 |
| OpenGL | 4.4 |
| OpenCL | 2.0 |
| HDMI | 1.4 |
| DP | 1.2 |
| eDP | 1.3 |
| Max HDMI Res | 4096x2304 @24 Hz |
| Max DP Res | 4096x2304 @60 Hz |
| Max eDP Res | 4096x2304 @60 Hz |
| Intel Quick Sync Video | |
| Intel InTru 3D | |
| Intel Insider | |
| Intel WiDi (Wireless Display) | |
| Intel Clear Video | |
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-1333, DDR3L-1600, DDR4-1866, DDR4-2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max bandwidth | 34.1 GB/s |
| Max memory | 64 GB |
Expansions
Features
Facts about "Core i5-7400T - Intel"
| has feature | integrated gpu + |
| integrated gpu | Intel HD Graphics 630 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |