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Difference between revisions of "intel/celeron/3865u"
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− | '''Celeron 3865U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3865U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 1.8 GHz | + | '''Celeron 3865U''' is a {{arch|64}} [[dual-core]] budget [[x86]] mobile microprocessors introduced by [[Intel]] in early 2017. The 3865U, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 300 MHz with a burst frequency of 900 GHz. |
== Cache == | == Cache == |
Revision as of 19:43, 5 January 2017
Template:mpu Celeron 3865U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3865U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Facts about "Celeron 3865U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 3865U - Intel#io + |
device id | 0x5906 + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
integrated gpu | HD Graphics 610 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |