From WikiChip
Difference between revisions of "intel/core i3/i3-7100h"
Line 37: | Line 37: | ||
| chipset = Sunrise Point | | chipset = Sunrise Point | ||
| chipset 2 = Union Point | | chipset 2 = Union Point | ||
− | | core name = Kaby Lake | + | | core name = Kaby Lake H |
| core family = Core i3 | | core family = Core i3 | ||
| core model = 158 | | core model = 158 |
Revision as of 15:03, 5 January 2017
Template:mpu Core i3-7100H is a 64-bit dual-core low-end performance x86 mobile microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 3 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400. The i3-7100H incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with burst frequency of 950 MHz.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||
|
Graphics
Integrated Graphics Information
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Facts about "Core i3-7100H - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i3-7100H - Intel#io + |
device id | 0x591B + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, Small Business Advantage +, My WiFi Technology + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel identity protection technology support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel small business advantage support | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
integrated gpu | HD Graphics 630 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 950 MHz (0.95 GHz, 950,000 KHz) + |
integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | LPDDR3-2133 +, DDR3L-1600 + and DDR4-2400 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |