Difference between revisions of "intel/core i3/i3-7320"

Revision as of 18:43, 4 January 2017

Template:mpu Core i3-7320 is a 64-bit dual-core low-end performance x86 desktop microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 4.1 GHz with a TDP of 51 Watts, supports up to 64 GiB of dual-channel DDR4-2400. The i3-7320 incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with burst frequency of 1.15 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

128 KiB

131,072 B
0.125 MiB

L1I$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	4-way set associative	write-back

L3$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		2x2 MiB	16-way set associative	write-back

@@ Line 73: / Line 73: @@
 == Cache ==
-{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
+{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
-{{cache info
+{{cache size
+|l1 cache=128 KiB
 |l1i cache=64 KiB
 |l1i break=2x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core, write-back)
+|l1i policy=write-back
 |l1d cache=64 KiB
 |l1d break=2x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core, write-back)
+|l1d policy=write-back
 |l2 cache=512 KiB
 |l2 break=2x256 KiB
 |l2 desc=4-way set associative
-|l2 extra=(per core, write-back)
+|l2 policy=write-back
 |l3 cache=4 MiB
-|l3 desc=shared
+|l3 break=2x2 MiB
+|l3 desc=16-way set associative
+|l3 policy=write-back
 }}

l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 18:43, 4 January 2017

Cache