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Difference between revisions of "intel/core i3/i3-7101e"
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'''Core i3-7101E''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] microprocessor introduced by [[Intel]] in early [[2017]] for the desktop and embedded market. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14 nm+ process]]. This processor, which has a base frequency of 3.9 GHz with a TDP of 54 Watts, supports up to 64 GiB of dual-channel DDR4-2133. The i3-7101E incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 350 MHz with burst frequency of 1.1 GHz.
 
'''Core i3-7101E''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] microprocessor introduced by [[Intel]] in early [[2017]] for the desktop and embedded market. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14 nm+ process]]. This processor, which has a base frequency of 3.9 GHz with a TDP of 54 Watts, supports up to 64 GiB of dual-channel DDR4-2133. The i3-7101E incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 350 MHz with burst frequency of 1.1 GHz.
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== Cache ==
 +
{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
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{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i policy=write-back
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 MiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=3 MiB
 +
|l3 break=2x1.5 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 18:35, 4 January 2017

Template:mpu Core i3-7101E is a 64-bit dual-core low-end performance x86 microprocessor introduced by Intel in early 2017 for the desktop and embedded market. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 3.9 GHz with a TDP of 54 Watts, supports up to 64 GiB of dual-channel DDR4-2133. The i3-7101E incorporates Intel's HD Graphics 610 IGP operating at 350 MHz with burst frequency of 1.1 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 MiB
524,288 KiB
536,870,912 B
0.5 GiB
  2x256 KiB4-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB16-way set associativewrite-back
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Facts about "Core i3-7101E - Intel"
RDF feed
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB) +
l3$ description16-way set associative +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +