Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i3/i3-7100t"
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{{intel title|Core i3-7100T}} | {{intel title|Core i3-7100T}} | ||
{{mpu | {{mpu | ||
| − | |||
| name = Core i3-7100T | | name = Core i3-7100T | ||
| − | | no image = | + | | no image = Yes |
| image = | | image = | ||
| image size = | | image size = | ||
| Line 10: | Line 9: | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| model number = i3-7100T | | model number = i3-7100T | ||
| − | | part number = | + | | part number = BX80677I37100T |
| − | | part number 1 = | + | | part number 1 = BXC80677I37100T |
| − | | | + | | s-spec = SSR35P |
| − | | | + | | s-spec 2 = |
| market = Desktop | | market = Desktop | ||
| − | | first announced = | + | | first announced = January 3, 2017 |
| − | | first launched = 2017 | + | | first launched = January 3, 2017 |
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
| + | | release price = $117.00 | ||
| family = Core i3 | | family = Core i3 | ||
| − | | series = | + | | series = i3-7100 |
| locked = Yes | | locked = Yes | ||
| frequency = 3,400 MHz | | frequency = 3,400 MHz | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| bus type = DMI 3.0 | | bus type = DMI 3.0 | ||
| bus speed = | | bus speed = | ||
| bus rate = 8 GT/s | | bus rate = 8 GT/s | ||
| clock multiplier = 34 | | clock multiplier = 34 | ||
| − | |||
| − | |||
| − | |||
| cpuid = | | cpuid = | ||
| Line 45: | Line 33: | ||
| isa = x86-64 | | isa = x86-64 | ||
| microarch = Kaby Lake | | microarch = Kaby Lake | ||
| − | | platform = | + | | platform = Kaby Lake |
| − | | chipset = | + | | chipset = Sunrise Point |
| + | | chipset 2 = Union Point | ||
| core name = Kaby Lake S | | core name = Kaby Lake S | ||
| − | | core family = | + | | core family = Core i3 |
| − | | core model = | + | | core model = 158 |
| − | | core stepping = | + | | core stepping = S0 |
| + | | core stepping 2 = | ||
| process = 14 nm | | process = 14 nm | ||
| transistors = | | transistors = | ||
| Line 57: | Line 47: | ||
| die width = | | die width = | ||
| die length = | | die length = | ||
| − | | word size = | + | | word size = 64 bit |
| core count = 2 | | core count = 2 | ||
| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 64 | + | | max memory = 64 GiB |
| − | |||
| electrical = Yes | | electrical = Yes | ||
| − | + | | v core min = 0.55 V | |
| − | | v core | + | | v core max = 1.52 V |
| − | | v core | ||
| − | |||
| − | |||
| sdp = | | sdp = | ||
| − | | tdp = | + | | tdp = 35 W |
| − | | | + | | tdp typical = |
| − | | | + | | ctdp down = |
| − | | tjunc min = | + | | ctdp down frequency = 2,400 MHz |
| − | | tjunc max = | + | | tjunc min = 0 °C |
| − | | tcase min = | + | | tjunc max = 92 °C |
| − | | tcase max = | + | | tcase min = |
| − | | tstorage min = | + | | tcase max = |
| − | | | + | | tstorage min = -25 °C |
| + | | tstorage max = 125 °C | ||
| + | | tambient min = | ||
| + | | tambient max = | ||
| − | + | | package module 1 = {{packages/intel/lga-1151}} | |
| − | | package | ||
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| − | |||
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}} | }} | ||
The '''Core i3-7100''' is a {{arch|64}} [[dual-core]] [[x86]] low-end [[microprocessor]] set to be introduced by [[Intel]] in early 2017. This processor operates at 3.4 GHz. | The '''Core i3-7100''' is a {{arch|64}} [[dual-core]] [[x86]] low-end [[microprocessor]] set to be introduced by [[Intel]] in early 2017. This processor operates at 3.4 GHz. | ||
Revision as of 17:19, 4 January 2017
Template:mpu The Core i3-7100 is a 64-bit dual-core x86 low-end microprocessor set to be introduced by Intel in early 2017. This processor operates at 3.4 GHz.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Kaby Lake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
2x256 KiB 4-way set associative (per core, write-back) |
| L3$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
shared |
Facts about "Core i3-7100T - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | shared + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |