From WikiChip
Difference between revisions of "socionext/sc2a11"
< socionext

Line 38: Line 38:
 
| platform            =  
 
| platform            =  
 
| chipset            =  
 
| chipset            =  
−
| core name          =  
+
| core name          = Cortex-A53
−
| core family        = Cortex-A53
+
| core family        =  
 
| core model          =  
 
| core model          =  
 
| core stepping      =  
 
| core stepping      =  

Revision as of 03:20, 4 December 2016

Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=socionext/sc2a11&oldid=30350"