Semiconductor & Computer Engineering
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Difference between revisions of "socionext/sc2a11"
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{{socionext title|SC2A11}} | {{socionext title|SC2A11}} | ||
| + | {{mpu | ||
| + | | name = Socionext SC2A11 | ||
| + | | no image = Yes | ||
| + | | image = | ||
| + | | image size = | ||
| + | | caption = | ||
| + | | designer = Socionext | ||
| + | | designer 2 = ARM Holdings | ||
| + | | manufacturer = | ||
| + | | model number = SC2A11 | ||
| + | | part number = | ||
| + | | part number 1 = | ||
| + | | part number 2 = | ||
| + | | part number 3 = | ||
| + | | market = Server | ||
| + | | market 2 = Networking | ||
| + | | market 3 = IoT | ||
| + | | first announced = November 14, 2016 | ||
| + | | first launched = | ||
| + | | last order = | ||
| + | | last shipment = | ||
| + | | release price = | ||
| + | |||
| + | | family = | ||
| + | | series = | ||
| + | | locked = | ||
| + | | frequency = 1,000 MHz | ||
| + | | bus type = AMBA | ||
| + | | bus speed = <!-- (Property::bus speed) --> | ||
| + | | bus rate = <!-- (Property::bus rate) --> | ||
| + | | bus links = <!-- ?x bus rate --> | ||
| + | | clock multiplier = | ||
| + | |||
| + | | isa family = ARM | ||
| + | | isa = ARMv8 | ||
| + | | microarch = Cortex-A53 | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = | ||
| + | | core family = Cortex-A53 | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | transistors = | ||
| + | | technology = CMOS | ||
| + | | die area = <!-- XX mm² --> | ||
| + | | die width = | ||
| + | | die length = | ||
| + | | word size = 64 bit | ||
| + | | core count = 24 | ||
| + | | thread count = 24 | ||
| + | | max cpus = | ||
| + | | max memory = | ||
| + | |||
| + | | electrical = <!-- put Yes if electrical info is added --> | ||
| + | | power = <!-- power consumption --> | ||
| + | | v core = | ||
| + | | v core tolerance = | ||
| + | | v io = | ||
| + | | v io tolerance = | ||
| + | | v io 2 = <!-- OR ... --> | ||
| + | | v io 3 = | ||
| + | | sdp = | ||
| + | | tdp = | ||
| + | | tdp typical = | ||
| + | | ctdp down = | ||
| + | | ctdp down frequency = | ||
| + | | ctdp up = | ||
| + | | ctdp up frequency = | ||
| + | | temp min = <!-- use TJ/TC whenever possible instead --> | ||
| + | | temp max = | ||
| + | | tjunc min = <!-- .. °C --> | ||
| + | | tjunc max = | ||
| + | | tcase min = | ||
| + | | tcase max = | ||
| + | | tstorage min = | ||
| + | | tstorage max = | ||
| + | | tambient min = | ||
| + | | tambient max = | ||
| + | |||
| + | | package module 1 = | ||
| + | | package module 2 = | ||
| + | |||
| + | | packaging = <!-- put Yes if packaging info is added --> | ||
| + | | package 0 = | ||
| + | | package 0 type = | ||
| + | | package 0 pins = | ||
| + | | package 0 pitch = | ||
| + | | package 0 width = | ||
| + | | package 0 length = | ||
| + | | package 0 height = | ||
| + | | socket 0 = | ||
| + | | socket 0 type = | ||
| + | }} | ||
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory. | '''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory. | ||
Revision as of 03:19, 4 December 2016
Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.