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Difference between revisions of "intel/xeon e7/e7-4820"
< intel‎ | xeon e7

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== Features ==  
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== Features ==
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{{mpu features
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{{x86 features
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| em64t      = Yes
+
|real=Yes
−
| nx          = Yes
+
|protected=Yes
−
| txt        = Yes
+
|smm=Yes
−
| tsx        =  
+
|fpu=Yes
−
| vpro        =  
+
|x8616=Yes
−
| ht          = Yes
+
|x8632=Yes
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| tbt1        = Yes
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|x8664=Yes
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| tbt2        =
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|nx=Yes
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| bpt        =  
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|3dnow=No
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| vt-x        = Yes
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|e3dnow=No
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| vt-d        = yes
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|mmx=Yes
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| ept        = Yes
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|emmx=Yes
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| mmx        = Yes
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|sse=Yes
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| sse         = Yes
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|sse2=Yes
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| sse2       = Yes
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|sse3=Yes
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| sse3       = Yes
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|ssse3=Yes
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| ssse3       = Yes
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|sse41=Yes
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| sse4.1      = Yes
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|sse42=Yes
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| sse4.2      = Yes
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|sse4a=No
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| aes        = Yes
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|avx=No
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| pclmul      =  
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|avx2=No
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| avx        =  
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|avx512=No
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| avx2        =  
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|abm=No
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| bmi        =  
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|tbm=No
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| bmi1       =  
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|bmi1=No
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| bmi2       =  
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|bmi2=No
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| f16c       =  
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|fma3=No
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| fma3        =  
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|fma4=No
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| mpx         =  
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|aes=Yes
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| sgx         =  
+
|rdrand=No
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| eist        = Yes
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|sha=No
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| secure key  =  
+
|xop=No
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| os guard    =  
+
|adx=No
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| intel at    =  
+
|clmul=No
 +
|f16c=No
 +
|tbt1=Yes
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 
}}
 
}}

Revision as of 02:13, 2 December 2016

Template:mpu Xeon E7-4820 is a 64-bit octa-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associativewrite-back
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  8x256 KiB8-way set associativewrite-back
L3$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  8x2.25 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels4
Max Bandwidth31.77 GiB/s
32,532.48 MiB/s
34.113 GB/s
34,112.778 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 7.942 GiB/s
Double 15.88 GiB/s
Triple 23.83 GiB/s
Quad 31.77 GiB/s
Physical Address (PAE)44 bit

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 1.0Turbo Boost Technology 1.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e7/e7-4820&oldid=30052"
Facts about "Xeon E7-4820 - Intel"
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has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 1 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description16-way set associative +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
max memory bandwidth31.77 GiB/s (32,532.48 MiB/s, 34.113 GB/s, 34,112.778 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels4 +
supported memory typeDDR3-1066 +