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Difference between revisions of "intel/xeon e7/e7-4807"
< intel‎ | xeon e7

(→‎Cache)
(→‎Memory controller)
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== Memory controller ==
 
== Memory controller ==
−
{{integrated memory controller
+
{{memory controller
−
| type               = DDR3-800
+
|type=DDR3-800
−
| controllers       = 1
+
|ecc=Yes
−
| channels           = 4
+
|max mem=1 TiB
−
| ecc support        = Yes
+
|controllers=1
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| max bandwidth     =  
+
|channels=4
−
| bandwidth schan    =  
+
|max bandwidth=23.84 GiB/s
−
| bandwidth dchan    =  
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|bandwidth schan=5.96 GiB/s
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| max memory        = 2048 GB
+
|bandwidth dchan=11.92 GiB/s
 +
|bandwidth tchan=17.88 GiB/s
 +
|bandwidth qchan=23.84 GiB/s
 
}}
 
}}
  

Revision as of 02:06, 2 December 2016

Template:mpu Xeon E7-4807 is a 64-bit hexa-core x86 data center microprocessor that supports up to 4 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.86 GHz with 95 W TDP but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB4-way set associativewrite-back
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  6x256 KiB8-way set associativewrite-back
L3$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  6x3 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem1 TiB
Controllers1
Channels4
Max Bandwidth23.84 GiB/s
24,412.16 MiB/s
25.598 GB/s
25,598.005 MB/s
0.0233 TiB/s
0.0256 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s
Triple 17.88 GiB/s
Quad 23.84 GiB/s

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e7/e7-4807&oldid=30042"
Facts about "Xeon E7-4807 - Intel"
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has ecc memory supporttrue +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description4-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description16-way set associative +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
max memory bandwidth23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels4 +
supported memory typeDDR3-800 +