From WikiChip
Difference between revisions of "intel/xeon e7/e7-4860"
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== Memory controller == | == Memory controller == | ||
− | {{ | + | {{memory controller |
− | | type | + | |type=DDR3-1066 |
− | | | + | |ecc=Yes |
− | | | + | |max mem=2 TiB |
− | | controllers | + | |controllers=1 |
− | | channels | + | |channels=4 |
− | | | + | |max bandwidth=31.77 GiB/s |
− | | | + | |bandwidth schan=7.942 GiB/s |
− | | bandwidth | + | |bandwidth dchan=15.88 GiB/s |
− | | bandwidth | + | |bandwidth tchan=23.83 GiB/s |
− | | | + | |bandwidth qchan=31.77 GiB/s |
+ | |pae=44 bit | ||
}} | }} | ||
Revision as of 03:02, 2 December 2016
Template:mpu Xeon E7-4860 is a 64-bit deca-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.26 GHz with turob frequency of 2.66 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
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Integrated Memory Controller
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Features
Facts about "Xeon E7-4860 - Intel"
has ecc memory support | true + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2.56 MiB (2,621.44 KiB, 2,684,354.56 B, 0.0025 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
max memory bandwidth | 31.77 GiB/s (32,532.48 MiB/s, 34.113 GB/s, 34,112.778 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 4 + |
supported memory type | DDR3-1066 + |