From WikiChip
Difference between revisions of "intel/xeon e7/e7-2803"
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== Cache == | == Cache == | ||
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
− | {{cache | + | {{cache size |
+ | |l1 cache = 384 KiB | ||
|l1i cache=192 KiB | |l1i cache=192 KiB | ||
|l1i break=6x32 KiB | |l1i break=6x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
− | |l1i | + | |l1i policy=write-back |
|l1d cache=192 KiB | |l1d cache=192 KiB | ||
|l1d break=6x32 KiB | |l1d break=6x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l1d | + | |l1d policy=write-back |
|l2 cache=1.5 MiB | |l2 cache=1.5 MiB | ||
|l2 break=6x256 KiB | |l2 break=6x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
− | |l2 | + | |l2 policy=write-back |
|l3 cache=18 MiB | |l3 cache=18 MiB | ||
+ | |l3 break=6x3 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
+ | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 00:35, 2 December 2016
Template:mpu Xeon E7-2803 is a 64-bit hexa-core x86 data center microprocessor that supports up to 2 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.73 GHz with a TDP of 105 W but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3-800 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max memory | 1024 GB |
Features
Facts about "Xeon E7-2803 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E7-2803 - Intel#package + |
base frequency | 1,733.33 MHz (1.733 GHz, 1,733,330 kHz) + |
bus rate | 4,800 MT/s (4.8 GT/s, 4,800,000 kT/s) + |
bus type | QPI + |
chipset | Boxboro + |
clock multiplier | 13 + |
core count | 6 + |
core family | 6 + |
core model | 47 + |
core name | Westmere EX + |
core stepping | A2 + |
core voltage | 1.35 V (13.5 dV, 135 cV, 1,350 mV) + |
cpuid | 206F2 + |
designer | Intel + |
die area | 513 mm² (0.795 in², 5.13 cm², 513,000,000 µm²) + |
family | Xeon E7 + |
first announced | April 5, 2011 + |
first launched | April 5, 2011 + |
full page name | intel/xeon e7/e7-2803 + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
last order | August 21, 2015 + |
last shipment | February 2, 2018 + |
ldate | April 5, 2011 + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 337.15 K (64 °C, 147.2 °F, 606.87 °R) + |
max cpu count | 2 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
max memory channels | 4 + |
max storage temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
microarchitecture | Westmere + |
min case temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | E7-2803 + |
name | Xeon E7-2803 + |
package | FCLGA-8 + |
part number | AT80615006438AB + |
platform | Boxboro + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
release price | $ 774.00 (€ 696.60, £ 626.94, ¥ 79,977.42) + |
s-spec | SLC3M + |
series | E7-2800 + |
smp max ways | 2 + |
supported memory type | DDR3-800 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 12 + |
transistor count | 2,600,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |