From WikiChip
Difference between revisions of "intel/xeon e7/e7-4870"
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== Cache == | == Cache == | ||
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
− | {{cache | + | {{cache size |
+ | |l1 cache = 640 KiB | ||
|l1i cache=320 KiB | |l1i cache=320 KiB | ||
|l1i break=10x32 KiB | |l1i break=10x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
− | |l1i | + | |l1i policy=write-back |
|l1d cache=320 KiB | |l1d cache=320 KiB | ||
|l1d break=10x32 KiB | |l1d break=10x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l1d | + | |l1d policy=write-back |
|l2 cache=2.56 MiB | |l2 cache=2.56 MiB | ||
|l2 break=10x256 KiB | |l2 break=10x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
− | |l2 | + | |l2 policy=write-back |
|l3 cache=30 MiB | |l3 cache=30 MiB | ||
+ | |l3 break=10x3 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
+ | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 01:35, 2 December 2016
Template:mpu Xeon E7-4870 is a 64-bit deca-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.4 GHz with turob frequency of 2.8 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3-800, DDR3-978, DDR3-1066 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max memory | 2048 GB |
Features
Facts about "Xeon E7-4870 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E7-4870 - Intel#package + |
base frequency | 2,399.99 MHz (2.4 GHz, 2,399,990 kHz) + |
bus rate | 6,400 MT/s (6.4 GT/s, 6,400,000 kT/s) + |
bus type | QPI + |
chipset | Boxboro + |
clock multiplier | 18 + |
core count | 10 + |
core family | 6 + |
core model | 47 + |
core name | Westmere EX + |
core stepping | A2 + |
core voltage | 1.35 V (13.5 dV, 135 cV, 1,350 mV) + |
cpuid | 206F2 + |
designer | Intel + |
die area | 513 mm² (0.795 in², 5.13 cm², 513,000,000 µm²) + |
family | Xeon E7 + |
first announced | April 5, 2011 + |
first launched | April 5, 2011 + |
full page name | intel/xeon e7/e7-4870 + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 1 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2.56 MiB (2,621.44 KiB, 2,684,354.56 B, 0.0025 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |
last order | August 21, 2015 + |
last shipment | February 5, 2016 + |
ldate | April 5, 2011 + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 342.15 K (69 °C, 156.2 °F, 615.87 °R) + |
max cpu count | 4 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 31.77 GiB/s (32,532.48 MiB/s, 34.113 GB/s, 34,112.778 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 4 + |
max storage temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
microarchitecture | Westmere + |
min case temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | E7-4870 + |
name | Xeon E7-4870 + |
package | FCLGA-8 + |
part number | AT80615007263AA + and BX80615E74870 + |
platform | Boxboro + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
release price | $ 4,394.00 (€ 3,954.60, £ 3,559.14, ¥ 454,032.02) + |
s-spec | SLC3T + |
series | E7-4800 + |
smp max ways | 4 + |
supported memory type | DDR3-1066 + |
tdp | 130 W (130,000 mW, 0.174 hp, 0.13 kW) + |
technology | CMOS + |
thread count | 20 + |
transistor count | 2,600,000,000 + |
turbo frequency (10 cores) | 2,533.33 MHz (2.533 GHz, 2,533,330 kHz) + |
turbo frequency (1 core) | 2,799.99 MHz (2.8 GHz, 2,799,990 kHz) + |
turbo frequency (2 cores) | 2,799.99 MHz (2.8 GHz, 2,799,990 kHz) + |
turbo frequency (3 cores) | 2,799.99 MHz (2.8 GHz, 2,799,990 kHz) + |
turbo frequency (4 cores) | 2,799.99 MHz (2.8 GHz, 2,799,990 kHz) + |
turbo frequency (5 cores) | 2,666.66 MHz (2.667 GHz, 2,666,660 kHz) + |
turbo frequency (6 cores) | 2,666.66 MHz (2.667 GHz, 2,666,660 kHz) + |
turbo frequency (7 cores) | 2,533.33 MHz (2.533 GHz, 2,533,330 kHz) + |
turbo frequency (8 cores) | 2,533.33 MHz (2.533 GHz, 2,533,330 kHz) + |
turbo frequency (9 cores) | 2,533.33 MHz (2.533 GHz, 2,533,330 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |