From WikiChip
Difference between revisions of "intel/core i7/i7-660ue"
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{{memory controller | {{memory controller | ||
|type=DDR3-800 | |type=DDR3-800 | ||
+ | |ecc=Yes | ||
+ | |max mem=8 GiB | ||
|controllers=1 | |controllers=1 | ||
|channels=2 | |channels=2 | ||
− | |||
|max bandwidth=11.92 GiB/s | |max bandwidth=11.92 GiB/s | ||
− | |||
|bandwidth schan=5.96 GiB/s | |bandwidth schan=5.96 GiB/s | ||
|bandwidth dchan=11.92 GiB/s | |bandwidth dchan=11.92 GiB/s | ||
|pae=36 bit | |pae=36 bit | ||
}} | }} |
Revision as of 16:36, 27 November 2016
Template:mpu Core i7-660UE is a 64-bit dual-core x86-64 mobile microprocessor designed by Intel and introduced in early 2010. This chip is a first-generation Core i7 processor based on the Westmere microarchitecture and is manufactured on a 32 nm process. This processor operated at a based frequency of 1.33 GHz with a turbo frequency of 2.4 GHz and a TDP of 18 W. This MPU came with a HD Graphics (Ironlake) IGP operating at 166 MHz with a max burst frequency of 500 MHz.
Cache
- Main article: Westmere § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Facts about "Core i7-660UE - Intel"
has ecc memory support | true + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-800 + |