Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:cache size"
| Line 11: | Line 11: | ||
<table class="tl1" style="margin-left: 10px;"><!-- | <table class="tl1" style="margin-left: 10px;"><!-- | ||
-->{{#if: {{{l1 cache|}}} | <tr><th style="min-width: 35px;">L1$</th><td>[[l1$ size::{{{l1 cache}}}]]</td><td><table><!-- | -->{{#if: {{{l1 cache|}}} | <tr><th style="min-width: 35px;">L1$</th><td>[[l1$ size::{{{l1 cache}}}]]</td><td><table><!-- | ||
| − | -->{{#if: {{{l1i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">[[l1i$ size::{{{l1i cache}}}]]</td><td style="min-width: | + | -->{{#if: {{{l1i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">[[l1i$ size::{{{l1i cache}}}]]</td><td style="min-width: 75px;">{{{l1i break}}}</td><td style="min-width: 175px;">[[l1i$ description::{{{l1i desc}}}]]</td><td>{{{l1i policy}}}</td></tr> }}<!-- |
| − | -->{{#if: {{{l1d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>[[l1d$ size::{{{l1d cache}}}]]</td><td>{{{l1d break}}}</td><td style="min-width: 175px;">[[l1d$ description::{{{l1d desc}}}]]</td><td>{{{l1d policy}}}</td></tr> }}<!-- | + | -->{{#if: {{{l1d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>[[l1d$ size::{{{l1d cache}}}]]</td><td style="min-width: 75px;">{{{l1d break}}}</td><td style="min-width: 175px;">[[l1d$ description::{{{l1d desc}}}]]</td><td>{{{l1d policy}}}</td></tr> }}<!-- |
| − | -->{{#if: {{#if:{{{l1i cache|}}}{{{l1d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td>{{{l1 break}}}</td><td style="min-width: 175px;">{{#if: {{{l1 desc|}}} | [[l1$ description::{{{l1 desc}}}]] | }}</td><td>{{{l1 policy}}}</td></tr> }}<!-- | + | -->{{#if: {{#if:{{{l1i cache|}}}{{{l1d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l1 break}}}</td><td style="min-width: 175px;">{{#if: {{{l1 desc|}}} | [[l1$ description::{{{l1 desc}}}]] | }}</td><td>{{{l1 policy}}}</td></tr> }}<!-- |
--></table></td></tr> }}<!-- | --></table></td></tr> }}<!-- | ||
-->{{#if: {{{l2 cache|}}} | <tr><th style="min-width: 35px;">L2$</th><td>[[l2$ size::{{{l2 cache}}}]]</td><td><table><!-- | -->{{#if: {{{l2 cache|}}} | <tr><th style="min-width: 35px;">L2$</th><td>[[l2$ size::{{{l2 cache}}}]]</td><td><table><!-- | ||
-->{{#if: {{{l2i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">[[l2i$ size::{{{l2i cache}}}]]</td><td style="min-width: 75px;">{{{l2i break}}}</td><td style="min-width: 175px;">[[l2i$ description::{{{l2i desc}}}]]</td><td>{{{l2i policy}}}</td></tr> }}<!-- | -->{{#if: {{{l2i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">[[l2i$ size::{{{l2i cache}}}]]</td><td style="min-width: 75px;">{{{l2i break}}}</td><td style="min-width: 175px;">[[l2i$ description::{{{l2i desc}}}]]</td><td>{{{l2i policy}}}</td></tr> }}<!-- | ||
| − | -->{{#if: {{{l2d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>[[l2d$ size::{{{l2d cache}}}]]</td><td>{{{l2d break}}}</td><td style="min-width: 175px;">{{#if: {{{l2d desc|}}} | [[l2d$ description::{{{l2d desc}}}]] | }}</td><td>{{{l2d policy}}}</td></tr> }}<!-- | + | -->{{#if: {{{l2d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>[[l2d$ size::{{{l2d cache}}}]]</td><td style="min-width: 75px;">{{{l2d break}}}</td><td style="min-width: 175px;">{{#if: {{{l2d desc|}}} | [[l2d$ description::{{{l2d desc}}}]] | }}</td><td>{{{l2d policy}}}</td></tr> }}<!-- |
| − | -->{{#if: {{#if: {{{l2i cache|}}}{{{l2d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td>{{{l2 break}}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l2$ description::{{{l2 desc}}}]] | }}</td><td>{{{l2 policy}}}</td></tr> }}<!-- | + | -->{{#if: {{#if: {{{l2i cache|}}}{{{l2d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l2 break}}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l2$ description::{{{l2 desc}}}]] | }}</td><td>{{{l2 policy}}}</td></tr> }}<!-- |
--></table></td></tr> }}<!-- | --></table></td></tr> }}<!-- | ||
-->{{#if: {{{l3 cache|}}} | <tr><th style="min-width: 35px;">L3$</th><td>[[l3$ size::{{{l3 cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l13 break}}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l3$ description::{{{l3 desc}}}]] | }}</td><td>{{{l3 policy}}}</td></tr></table></td></tr> }}<!-- | -->{{#if: {{{l3 cache|}}} | <tr><th style="min-width: 35px;">L3$</th><td>[[l3$ size::{{{l3 cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l13 break}}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l3$ description::{{{l3 desc}}}]] | }}</td><td>{{{l3 policy}}}</td></tr></table></td></tr> }}<!-- | ||
Revision as of 09:24, 26 November 2016
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|
|
|
||