Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e5/e5-2699r v4"
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| − | | first announced = | + | | first announced = October 25, 2016 |
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Revision as of 17:22, 5 November 2016
Template:mpu The Xeon E5-2699R v4 is a 64-bit docosa-core x86 microprocessor introduced by Intel in 2016. This embedded server MPU is designed for low-power 2S environments. Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 704 KiB 720,896 B 0.688 MiB |
22x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 704 KiB 720,896 B 0.688 MiB |
22x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 5.5 MiB 5,632 KiB 5,767,168 B 0.00537 GiB |
22x256 KiB 8-way set associative (per core, write-back) |
| L3$ | 55 MiB 56,320 KiB 57,671,680 B 0.0537 GiB |
22x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR4-2400 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max bandwidth | 71.53 GiB/s |
| Bandwidth (single) | 17.88 GiB/s |
| Bandwidth (dual) | 35.76 GiB/s |
| Max memory | 1,536 GiB |
| Physical Address Extensions | 46 bit |
Expansions
Features
Facts about "Xeon E5-2699R v4 - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 704 KiB (720,896 B, 0.688 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 704 KiB (720,896 B, 0.688 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) + |