From WikiChip
Difference between revisions of "intel/xeon e5/e5-2623 v4"
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Revision as of 01:55, 5 November 2016
Template:mpu The Xeon E5-2623 v4 is a 64-bit quad-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (1U square form factor). Operating at 2.6 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
4x256 KiB 8-way set associative (per core, write-back) |
L3$ | 10 MiB 10,240 KiB 10,485,760 B 0.00977 GiB |
4x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR4-2133 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 63.58 GiB/s |
Bandwidth (single) | 15.89 GiB/s |
Bandwidth (dual) | 31.79 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions
Features
Facts about "Xeon E5-2623 v4 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |