From WikiChip
					
    Difference between revisions of "intel/xeon e5/e5-2667 v4"    
                	
														|  (→Memory controller) |  (+features) | ||
| Line 120: | Line 120: | ||
| | max memory         = 1,536 GiB | | max memory         = 1,536 GiB | ||
| | pae                = 46 bit | | pae                = 46 bit | ||
| + | }} | ||
| + | |||
| + | == Features ==  | ||
| + | {{mpu features | ||
| + | | em64t       = Yes | ||
| + | | nx          = Yes | ||
| + | | txt         = Yes | ||
| + | | tsx         = Yes | ||
| + | | vpro        = Yes | ||
| + | | ht          = Yes | ||
| + | | tbt1        =  | ||
| + | | tbt2        = Yes | ||
| + | | tbmt3       =  | ||
| + | | bpt         =  | ||
| + | | vt-x        = Yes | ||
| + | | vt-d        = Yes | ||
| + | | ept         = Yes | ||
| + | | mmx         = Yes | ||
| + | | sse         = Yes | ||
| + | | sse2        = Yes | ||
| + | | sse3        = Yes | ||
| + | | ssse3       = Yes | ||
| + | | sse4.1      = Yes | ||
| + | | sse4.2      = Yes | ||
| + | | aes         = Yes | ||
| + | | pclmul      = Yes | ||
| + | | avx         = Yes | ||
| + | | avx2        = Yes | ||
| + | | bmi         = Yes | ||
| + | | bmi1        = Yes | ||
| + | | bmi2        = Yes | ||
| + | | f16c        = Yes | ||
| + | | fma3        = Yes | ||
| + | | mpx         =  | ||
| + | | sgx         =  | ||
| + | | eist        = Yes | ||
| + | | secure key  = Yes | ||
| + | | os guard    = Yes | ||
| + | | intel at    =  | ||
| + | | intel ipt   =  | ||
| }} | }} | ||
Revision as of 19:23, 3 November 2016
Template:mpu The Xeon E5-2667 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).
Contents
Cache
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 256 KiB 262,144 B  0.25 MiB | 8x32 KiB 8-way set associative (per core, write-back) | 
| L1D$ | 256 KiB 262,144 B  0.25 MiB | 8x32 KiB 8-way set associative (per core, write-back) | 
| L2$ | 2 MiB 2,048 KiB  2,097,152 B 0.00195 GiB | 8x256 KiB 8-way set associative (per core, write-back) | 
| L3$ | 25 MiB 25,600 KiB  26,214,400 B 0.0244 GiB | 8x3.125 MiB 20-way set associative (shared, per core, write-back) | 
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR4-2400 | 
| Controllers | 1 | 
| Channels | 4 | 
| ECC Support | Yes | 
| Max bandwidth | 71.53 GiB/s | 
| Bandwidth (single) | 17.88 GiB/s | 
| Bandwidth (dual) | 35.76 GiB/s | 
| Max memory | 1,536 GiB | 
| Physical Address Extensions | 46 bit | 
Features
Facts about "Xeon E5-2667 v4  - Intel"
| l1d$ description | 8-way set associative + | 
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l2$ description | 8-way set associative + | 
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + | 
| l3$ description | 20-way set associative + | 
| l3$ size | 25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) + |