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Difference between revisions of "intel/xeon e5/e5-2698 v4"
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The '''Xeon E5-2698 v4''' is a {{arch|64}} [[icosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-2698 v4''' is a {{arch|64}} [[icosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
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== Cache ==
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
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{{cache info
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|l1i cache=640 KiB
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|l1i break=20x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=640 KiB
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|l1d break=20x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=5 MiB
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|l2 break=20x256 KiB
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|l2 desc=8-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=50 MiB
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|l3 break=20x2.5 MiB
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|l3 desc=20-way set associative
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|l3 extra=(shared, per core, write-back)
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}}

Revision as of 12:12, 3 November 2016

Template:mpu The Xeon E5-2698 v4 is a 64-bit icosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 640 KiB
655,360 B
0.625 MiB
20x32 KiB 8-way set associative (per core, write-back)
L1D$ 640 KiB
655,360 B
0.625 MiB
20x32 KiB 8-way set associative (per core, write-back)
L2$ 5 MiB
5,120 KiB
5,242,880 B
0.00488 GiB
20x256 KiB 8-way set associative (per core, write-back)
L3$ 50 MiB
51,200 KiB
52,428,800 B
0.0488 GiB
20x2.5 MiB 20-way set associative (shared, per core, write-back)
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description8-way set associative +
l2$ size5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ description20-way set associative +
l3$ size50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) +