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    Difference between revisions of "intel/xeon e5/e5-2667 v4"    
                	
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| The '''Xeon E5-2667 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | The '''Xeon E5-2667 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | ||
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=256 KiB | ||
| + | |l1i break=8x32 KiB | ||
| + | |l1i desc=8-way set associative | ||
| + | |l1i extra=(per core, write-back) | ||
| + | |l1d cache=256 KiB | ||
| + | |l1d break=8x32 KiB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d extra=(per core, write-back) | ||
| + | |l2 cache=4 MiB | ||
| + | |l2 break=16x256 KiB | ||
| + | |l2 desc=8-way set associative | ||
| + | |l2 extra=(per core, write-back) | ||
| + | |l3 cache=40 MiB | ||
| + | |l3 break=16x2.5 MiB | ||
| + | |l3 desc=20-way set associative | ||
| + | |l3 extra=(shared, per core, write-back) | ||
| + | }} | ||
Revision as of 04:27, 3 November 2016
Template:mpu The Xeon E5-2667 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 256 KiB 262,144 B  0.25 MiB | 8x32 KiB 8-way set associative (per core, write-back) | 
| L1D$ | 256 KiB 262,144 B  0.25 MiB | 8x32 KiB 8-way set associative (per core, write-back) | 
| L2$ | 4 MiB 4,096 KiB  4,194,304 B 0.00391 GiB | 16x256 KiB 8-way set associative (per core, write-back) | 
| L3$ | 40 MiB 40,960 KiB  41,943,040 B 0.0391 GiB | 16x2.5 MiB 20-way set associative (shared, per core, write-back) | 
Facts about "Xeon E5-2667 v4  - Intel"
| l1d$ description | 8-way set associative + | 
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l2$ description | 8-way set associative + | 
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + | 
| l3$ description | 20-way set associative + | 
| l3$ size | 40 MiB (40,960 KiB, 41,943,040 B, 0.0391 GiB) + |