From WikiChip
Difference between revisions of "intel/core i5/i5-7500"
< intel‎ | core i5

(graphics)
(mem)
Line 168: Line 168:
 
| intel fdi          =  
 
| intel fdi          =  
 
| intel clear video  = Yes
 
| intel clear video  = Yes
 +
}}
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR3L-1333
 +
| type 2            = DDR3L-1600
 +
| type 3            = DDR4-1866
 +
| type 4            = DDR4-2133
 +
| controllers        = 1
 +
| channels          = 2
 +
| ecc support        = Yes
 +
| max bandwidth      = 34.1 GB/s
 +
| bandwidth schan    =
 +
| bandwidth dchan    =
 +
| bandwidth tchan    =
 +
| bandwidth qchan    =
 +
| max memory        = 64 GB
 +
}}
 +
 +
== Expansions ==
 +
{{mpu expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 16
 +
| pcie config        = 1x16
 +
| pcie config 1      = 2x8
 +
| pcie config 2      = 1x8+2x4
 +
| usb revision      =
 +
| usb revision 2    =
 +
| usb revision N    =
 +
| usb ports          =
 +
| sata ports        =
 +
| integrated lan    =
 +
| uart              =
 +
| gp io              =
 
}}
 
}}

Revision as of 22:30, 22 September 2016

Template:mpu The Core i5-7500 is a 64-bit x86 quad-core microprocessor based on Kaby Lake and is set to be introduced by Intel in late 2016. This MPU operates at 3.4 GHz with a TDP of 65 W.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 4-way set associative (per core, write-back)
L3$ 6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
shared

Graphics

Integrated Graphic Information
GPU Intel HD Graphics 630
Execution Units 24
Displays 3
Frequency  ? MHz
"? MHz" is not a number.
Max frequency  ? GHz
"? GHz" is not a number.
Max memory 64 GB
"GB" is not declared as a valid unit of measurement for this property.
Output DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX 12.1
OpenGL 4.4
OpenCL 2.0
HDMI 1.4
DP 1.2
eDP 1.3
Max HDMI Res 4096x2304 @24 Hz
Max DP Res 4096x2304 @60 Hz
Max eDP Res 4096x2304 @60 Hz
Intel Quick Sync Video
Intel InTru 3D
Intel Insider
Intel WiDi (Wireless Display)
Intel Clear Video

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1866, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max bandwidth 34.1 GB/s
Max memory 64 GB

Expansions

Template:mpu expansions

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-7500&oldid=25918"
Facts about "Core i5-7500 - Intel"
RDF feed
has featureintegrated gpu +
integrated gpuIntel HD Graphics 630 +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ descriptionshared +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +