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Difference between revisions of "intel/core i5/i5-7500"
< intel‎ | core i5

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{{unknown features}}
 
{{unknown features}}
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== Cache ==
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{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
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{{cache info
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|l1i cache=128 KiB
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|l1i break=4x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=128 KiB
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|l1d break=4x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=1 MiB
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|l2 break=4x256 KiB
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|l2 desc=4-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=6 MiB
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|l3 desc=shared
 +
}}

Revision as of 22:16, 22 September 2016

Template:mpu The Core i5-7500 is a 64-bit x86 quad-core microprocessor based on Kaby Lake and is set to be introduced by Intel in late 2016. This MPU operates at 3.4 GHz with a TDP of 65 W.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 4-way set associative (per core, write-back)
L3$ 6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
shared
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Facts about "Core i5-7500 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ descriptionshared +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +