Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/atom x3/x3-c3405"
(→Cache) |
|||
| Line 63: | Line 63: | ||
== Cache == | == Cache == | ||
{{cache info | {{cache info | ||
| − | |l2 cache=2 | + | |l2 cache=2 MiB |
| − | |l2 break=2x1 | + | |l2 break=2x1 MiB |
|l2 extra=(per 2 cores) | |l2 extra=(per 2 cores) | ||
|l3 cache=0 KiB | |l3 cache=0 KiB | ||
Revision as of 23:38, 20 September 2016
Template:mpu The x3-C3405 is a quad-core 64-bit system-on-chip designed by Intel and introduced in April 2015. This chip is identical to the x3-C3445 except for its networking capabilities which are limited to WiFi only. Operating in 1.2 GHz with a burst frequency of 1.4 GHz, this chip has a scenario designed power of 2 W. This chip is manufactured in 28 nm process and integrates an ARM Mali T720 MP2 GPU.
Contents
Cache
| Cache Info [Edit Values] | ||
| L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
2x1 MiB (per 2 cores) |
| L3$ | 0 KiB 0 MiB 0 B 0 GiB |
No L3$ |
Graphics
| Integrated Graphic Information | |
| GPU | Mali T720 MP2 |
| Displays | 1 |
| Frequency | 456 MHz 0.456 GHz
456,000 KHz |
| Output | DSI |
| DirectX | 9.3 |
| OpenGL ES | 3.0 |
| Max DSI Res | 1280x800 @60 Hz |
Memory controller
| Integrated Memory Controller | |
| Type | LPDDR2-1066, LPDDR3-1066 |
| Controllers | 1 |
| Channels | 1 |
| ECC Support | No |
| Max bandwidth | 4,200 MB/s |
| Max memory | 2,048 MB |
Input/Output
- USB Revision: 2.0 OTG
- USB Ports: 1
- GP I/O: 5x I2C
- UART: 7x USIF
- GLONASS
Storage
- eMMC 4.51
Features
Networking
- RF Transceiver: SMARTi 4.5s
- Wi-Fi: 802.11 B/G/N
- Protocol Stack: Intel Release 10 Protocol Stack
ISP/Camera
- Up to 13 MP/5 MP
Facts about "Atom x3-C3405 - Intel"
| has feature | integrated gpu + |
| integrated gpu | Mali T720 MP2 + |
| integrated gpu base frequency | 456 MHz (0.456 GHz, 456,000 KHz) + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| l3$ description | No L3$ + |
| l3$ size | 0 MiB (0 KiB, 0 B, 0 GiB) + |