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Difference between revisions of "amd/k6-2/k6-2-333afr-66"
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== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}}
 
{{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}}
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[[L2$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
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[[L2$]] can be 512 KiB to 2 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
 
{{cache info
 
{{cache info
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|l1i cache=32 KB
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|l1i cache=32 KiB
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|l1i break=1x32 KB
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|l1i break=1x32 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
 
|l1i extra=
 
|l1i extra=
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|l1d cache=32 KB
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|l1d cache=32 KiB
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|l1d break=1x32 KB
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|l1d break=1x32 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
 
|l1d extra=
 
|l1d extra=

Revision as of 23:20, 20 September 2016

Template:mpu K6-2/333AFR-66 was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 333 MHz with a FSB of 66 MHz consumed 19 W. Note that this is an identical model to K6-2/333AFR with a multiplier of 5 instead of 3.6 designed to support a 66 MHz bus instead of 95 MHz.

Cache

Main article: K6-2 § Cache

L2$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state

Documents

DataSheet

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-2/k6-2-333afr-66&oldid=25726"
Facts about "K6-2/333AFR-66 - AMD"
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l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +