Semiconductor & Computer Engineering
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Difference between revisions of "amd/duron/d800aut1b"
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{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1i cache=64 | + | |l1i cache=64 KiB |
| − | |l1i break=1x64 | + | |l1i break=1x64 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=64 | + | |l1d cache=64 KiB |
| − | |l1d break=1x64 | + | |l1d break=1x64 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=64 | + | |l2 cache=64 KiB |
| − | |l2 break=1x64 | + | |l2 break=1x64 KiB |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 extra= | |l2 extra= | ||
Revision as of 22:48, 20 September 2016
Template:mpu Duron 800 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2000. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 800 MHz with a bus capable of 200 MT/s with a typical TDP of 35.4 W.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Halt State
- Sleep State
Facts about "Duron 800 (Spitfire) - AMD"
| base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
| bus rate | 200 MT/s (0.2 GT/s, 200,000 kT/s) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 8 + |
| core count | 1 + |
| core family | 6 + |
| core model | 3 + |
| core name | Spitfire + |
| core stepping | 0 + |
| core voltage | 1.6 V (16 dV, 160 cV, 1,600 mV) + |
| core voltage tolerance | 0.1 V + |
| cpuid | 630 + |
| designer | AMD + |
| die area | 100 mm² (0.155 in², 1 cm², 100,000,000 µm²) + |
| family | Duron + |
| first announced | October 17, 2000 + |
| first launched | October 17, 2000 + |
| full page name | amd/duron/d800aut1b + |
| has feature | Halt State + and Sleep State + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
| ldate | October 17, 2000 + |
| main image |  + |
| manufacturer | AMD + |
| market segment | Desktop + |
| max case temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max storage temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
| microarchitecture | K7 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
| model number | Duron 800 + |
| name | Duron 800 + |
| part number | D800AUT1B + and D0800AUT1B + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |
| series | Duron Desktop + |
| smp max ways | 1 + |
| tdp | 35.4 W (35,400 mW, 0.0475 hp, 0.0354 kW) + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 25,000,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |
