Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486sx2-50"
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{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
|l1 extra=(unified, write-through policy) | |l1 extra=(unified, write-through policy) | ||
Revision as of 21:57, 20 September 2016
Template:mpu i486SX2-50 was a fourth-generation x86 microprocessor introduced by Intel in the early 1990s. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX line had no functional FPU on-die.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Gallery
A80486SX2-50, S-Spec SX845
.png)
See also
Facts about "i486SX2-50 - Intel"
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |